include/configs/da850evm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16 /* check if direct NOR boot config is used */
  17 #ifndef CONFIG_DIRECT_NOR_BOOT
  18 #define CONFIG_USE_SPIFLASH
  19 #endif
  20
  21 /*
  22 * Disable DM_* for SPL build and can be re-enabled after adding
  23 * DM support in SPL
  24 */
  25 #ifdef CONFIG_SPL_BUILD
  26 #undef CONFIG_DM_SPI
  27 #undef CONFIG_DM_SPI_FLASH
  28 #undef CONFIG_DM_I2C
  29 #undef CONFIG_DM_I2C_COMPAT
  30 #endif
  31 /*
  32  * SoC Configuration
  33  */
  34 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  35 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  36 #define CONFIG_SYS_OSCIN_FREQ           24000000
  37 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  38 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  39
  40 #ifdef CONFIG_DIRECT_NOR_BOOT
  41 #define CONFIG_ARCH_CPU_INIT
  42 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  43 #endif
  44
  45 /*
  46  * Memory Info
  47  */
  48 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  49 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  50 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  51 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  52
  53 /* memtest start addr */
  54 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  55
  56 /* memtest will be run on 16MB */
  57 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  58
  59 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  60         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  61         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  62         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  63         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  64         DAVINCI_SYSCFG_SUSPSRC_I2C)
  65
  66 /*
  67  * PLL configuration
  68  */
  69
  70 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  71 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  72
  73 /*
  74  * DDR2 memory configuration
  75  */
  76 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  77                                         DV_DDR_PHY_EXT_STRBEN | \
  78                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  79
  80 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  81         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  82         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  83         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  84         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  85         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  86         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  87         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  88
  89 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  90 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  91
  92 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  93         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  94         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  95         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  96         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  97         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  98         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  99         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
 100         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
 101
 102 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
 103         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
 104         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
 105         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
 106         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
 107         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
 108         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
 109         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
 110
 111 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
 112 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 113
 114 /*
 115  * Serial Driver info
 116  */
 117
 118 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT)
 119 #define CONFIG_SYS_NS16550_SERIAL
 120 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 121 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 122 #endif
 123 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 124
 125 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 126 #ifdef CONFIG_SPL_BUILD
 127 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
 128 #define CONFIG_SF_DEFAULT_SPEED         30000000
 129 #define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
 130 #endif
 131
 132 #ifdef CONFIG_USE_SPIFLASH
 133 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
 134 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x40000
 135 #endif
 136
 137 /*
 138  * I2C Configuration
 139  */
 140 #ifndef CONFIG_SPL_BUILD
 141 #define CONFIG_SYS_I2C_DAVINCI
 142 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 143 #endif
 144
 145 /*
 146  * Flash & Environment
 147  */
 148 #ifdef CONFIG_NAND
 149 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
 150 #define CONFIG_ENV_SIZE                 (128 << 10)
 151 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 152 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 153 #define CONFIG_SYS_NAND_PAGE_2K
 154 #define CONFIG_SYS_NAND_CS              3
 155 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 156 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 157 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 158 #undef CONFIG_SYS_NAND_HW_ECC
 159 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 160 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 161 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 162 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 163 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 164 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x28000
 165 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x60000
 166 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 167 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 168 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 169                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 170                                         CONFIG_SYS_MALLOC_LEN -       \
 171                                         GENERATED_GBL_DATA_SIZE)
 172 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 173                                 24, 25, 26, 27, 28, \
 174                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 175                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 176                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 177                                 59, 60, 61, 62, 63 }
 178 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 179 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 180 #define CONFIG_SYS_NAND_ECCSIZE         512
 181 #define CONFIG_SYS_NAND_ECCBYTES        10
 182 #define CONFIG_SYS_NAND_OOBSIZE         64
 183 #define CONFIG_SPL_NAND_BASE
 184 #define CONFIG_SPL_NAND_DRIVERS
 185 #define CONFIG_SPL_NAND_ECC
 186 #define CONFIG_SPL_NAND_LOAD
 187 #endif
 188
 189 /*
 190  * Network & Ethernet Configuration
 191  */
 192 #ifdef CONFIG_DRIVER_TI_EMAC
 193 #define CONFIG_BOOTP_DNS2
 194 #define CONFIG_BOOTP_SEND_HOSTNAME
 195 #define CONFIG_NET_RETRY_COUNT  10
 196 #endif
 197
 198 #ifdef CONFIG_USE_NOR
 199 #define CONFIG_FLASH_CFI_DRIVER
 200 #define CONFIG_SYS_FLASH_CFI
 201 #define CONFIG_SYS_FLASH_PROTECTION
 202 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 203 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 204 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_SECT_SZ * 3)
 205 #define CONFIG_ENV_SIZE                 (10 << 10) /* 10KB */
 206 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 207 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 208 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 209                + 3)
 210 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
 211 #endif
 212
 213 #ifdef CONFIG_USE_SPIFLASH
 214 #define CONFIG_ENV_SIZE                 (64 << 10)
 215 #define CONFIG_ENV_OFFSET               (512 << 10)
 216 #define CONFIG_ENV_SECT_SIZE            (64 << 10)
 217 #ifdef CONFIG_SPL_BUILD
 218 #undef CONFIG_SPI_FLASH_MTD
 219 #endif
 220 #endif
 221
 222 /*
 223  * U-Boot general configuration
 224  */
 225 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 226 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 227 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 228 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 229 #define CONFIG_MX_CYCLIC
 230
 231 /*
 232  * Linux Information
 233  */
 234 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 235 #define CONFIG_HWCONFIG         /* enable hwconfig */
 236 #define CONFIG_CMDLINE_TAG
 237 #define CONFIG_REVISION_TAG
 238 #define CONFIG_SETUP_MEMORY_TAGS
 239
 240 #define CONFIG_BOOTCOMMAND \
 241                 "run envboot; " \
 242                 "run mmcboot; "
 243
 244 #define DEFAULT_LINUX_BOOT_ENV \
 245         "loadaddr=0xc0700000\0" \
 246         "fdtaddr=0xc0600000\0" \
 247         "scriptaddr=0xc0600000\0"
 248
 249 #include <environment/ti/mmc.h>
 250
 251 #define CONFIG_EXTRA_ENV_SETTINGS \
 252         DEFAULT_LINUX_BOOT_ENV \
 253         DEFAULT_MMC_TI_ARGS \
 254         "bootpart=0:2\0" \
 255         "bootdir=/boot\0" \
 256         "bootfile=zImage\0" \
 257         "fdtfile=da850-evm.dtb\0" \
 258         "boot_fdt=yes\0" \
 259         "boot_fit=0\0" \
 260         "console=ttyS2,115200n8\0" \
 261         "hwconfig=dsp:wake=yes"
 262
 263 #ifdef CONFIG_CMD_BDI
 264 #define CONFIG_CLOCKS
 265 #endif
 266
 267 #if !defined(CONFIG_NAND) && \
 268         !defined(CONFIG_USE_NOR) && \
 269         !defined(CONFIG_USE_SPIFLASH)
 270 #define CONFIG_ENV_SIZE         (16 << 10)
 271 #endif
 272
 273 #ifndef CONFIG_DIRECT_NOR_BOOT
 274 /* defines for SPL */
 275 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 276                                                 CONFIG_SYS_MALLOC_LEN)
 277 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 278 #define CONFIG_SPL_STACK        0x8001ff00
 279 #define CONFIG_SPL_TEXT_BASE    0x80000000
 280 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 281 #define CONFIG_SPL_PAD_TO       32768
 282 #endif
 283
 284 /* Load U-Boot Image From MMC */
 285
 286 /* additions for new relocation code, must added to all boards */
 287 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 288
 289 #ifdef CONFIG_DIRECT_NOR_BOOT
 290 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 291 #else
 292 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 293                                         GENERATED_GBL_DATA_SIZE)
 294 #endif /* CONFIG_DIRECT_NOR_BOOT */
 295
 296 #include <asm/arch/hardware.h>
 297
 298 #endif /* __CONFIG_H */