include/configs/da850evm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16 /* check if direct NOR boot config is used */
  17 #ifndef CONFIG_DIRECT_NOR_BOOT
  18 #define CONFIG_USE_SPIFLASH
  19 #endif
  20
  21 /*
  22 * Disable DM_* for SPL build and can be re-enabled after adding
  23 * DM support in SPL
  24 */
  25 #ifdef CONFIG_SPL_BUILD
  26 #undef CONFIG_DM_SPI
  27 #undef CONFIG_DM_SPI_FLASH
  28 #undef CONFIG_DM_I2C
  29 #undef CONFIG_DM_I2C_COMPAT
  30 #endif
  31 /*
  32  * SoC Configuration
  33  */
  34 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  35 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  36 #define CONFIG_SYS_OSCIN_FREQ           24000000
  37 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  38 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  39 #define CONFIG_SKIP_LOWLEVEL_INIT
  40
  41 #ifdef CONFIG_DIRECT_NOR_BOOT
  42 #define CONFIG_ARCH_CPU_INIT
  43 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  44 #endif
  45
  46 /*
  47  * Memory Info
  48  */
  49 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  50 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  51 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  52 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  53
  54 /* memtest start addr */
  55 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  56
  57 /* memtest will be run on 16MB */
  58 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  59
  60 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  61         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  62         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  63         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  64         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  65         DAVINCI_SYSCFG_SUSPSRC_I2C)
  66
  67 /*
  68  * PLL configuration
  69  */
  70
  71 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  72 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  73
  74 /*
  75  * DDR2 memory configuration
  76  */
  77 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  78                                         DV_DDR_PHY_EXT_STRBEN | \
  79                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  80
  81 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  82         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  83         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  84         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  85         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  86         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  87         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  88         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  89
  90 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  91 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  92
  93 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  94         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  95         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  96         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  97         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  98         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  99         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
 100         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
 101         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
 102
 103 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
 104         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
 105         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
 106         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
 107         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
 108         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
 109         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
 110         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
 111
 112 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
 113 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 114
 115 /*
 116  * Serial Driver info
 117  */
 118
 119 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT)
 120 #define CONFIG_SYS_NS16550_SERIAL
 121 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
 122 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
 123 #endif
 124 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 125
 126 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 127 #ifdef CONFIG_SPL_BUILD
 128 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
 129 #define CONFIG_SF_DEFAULT_SPEED         30000000
 130 #define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
 131 #endif
 132
 133 #ifdef CONFIG_USE_SPIFLASH
 134 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
 135 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x40000
 136 #endif
 137
 138 /*
 139  * I2C Configuration
 140  */
 141 #ifndef CONFIG_SPL_BUILD
 142 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 143 #endif
 144
 145 /*
 146  * Flash & Environment
 147  */
 148 #ifdef CONFIG_NAND
 149 #ifdef CONFIG_ENV_IS_IN_NAND
 150 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
 151 #define CONFIG_ENV_SIZE                 (128 << 10)
 152 #define CONFIG_ENV_SECT_SIZE    (128 << 10)
 153 #endif
 154 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 155 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 156 #define CONFIG_SYS_NAND_PAGE_2K
 157 #define CONFIG_SYS_NAND_CS              3
 158 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 159 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 160 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 161 #undef CONFIG_SYS_NAND_HW_ECC
 162 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 163 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 164 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 165 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 166 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 167 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x40000
 168 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 169 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 170 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 171                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 172                                         CONFIG_SYS_MALLOC_LEN -       \
 173                                         GENERATED_GBL_DATA_SIZE)
 174 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 175                                 24, 25, 26, 27, 28, \
 176                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 177                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 178                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 179                                 59, 60, 61, 62, 63 }
 180 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 181 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 182 #define CONFIG_SYS_NAND_ECCSIZE         512
 183 #define CONFIG_SYS_NAND_ECCBYTES        10
 184 #define CONFIG_SYS_NAND_OOBSIZE         64
 185 #define CONFIG_SPL_NAND_BASE
 186 #define CONFIG_SPL_NAND_DRIVERS
 187 #define CONFIG_SPL_NAND_ECC
 188 #define CONFIG_SPL_NAND_LOAD
 189 #endif
 190
 191 /*
 192  * Network & Ethernet Configuration
 193  */
 194 #ifdef CONFIG_DRIVER_TI_EMAC
 195 #define CONFIG_BOOTP_DNS2
 196 #define CONFIG_BOOTP_SEND_HOSTNAME
 197 #define CONFIG_NET_RETRY_COUNT  10
 198 #endif
 199
 200 #ifdef CONFIG_USE_NOR
 201 #define CONFIG_FLASH_CFI_DRIVER
 202 #define CONFIG_SYS_FLASH_CFI
 203 #define CONFIG_SYS_FLASH_PROTECTION
 204 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 205 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 206 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_FLASH_SECT_SZ * 3)
 207 #define CONFIG_ENV_SIZE                 (10 << 10) /* 10KB */
 208 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 209 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 210 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 211                + 3)
 212 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
 213 #endif
 214
 215 #ifdef CONFIG_USE_SPIFLASH
 216 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 217 #define CONFIG_ENV_SIZE                 (64 << 10)
 218 #define CONFIG_ENV_OFFSET               (512 << 10)
 219 #define CONFIG_ENV_SECT_SIZE    (64 << 10)
 220 #endif
 221 #ifdef CONFIG_SPL_BUILD
 222 #undef CONFIG_SPI_FLASH_MTD
 223 #endif
 224 #endif
 225
 226 /*
 227  * U-Boot general configuration
 228  */
 229 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 230 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 231 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 232 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 233 #define CONFIG_MX_CYCLIC
 234
 235 /*
 236  * Linux Information
 237  */
 238 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 239 #define CONFIG_HWCONFIG         /* enable hwconfig */
 240 #define CONFIG_CMDLINE_TAG
 241 #define CONFIG_REVISION_TAG
 242 #define CONFIG_SETUP_MEMORY_TAGS
 243
 244 #define CONFIG_BOOTCOMMAND \
 245                 "run envboot; " \
 246                 "run mmcboot; "
 247
 248 #define DEFAULT_LINUX_BOOT_ENV \
 249         "loadaddr=0xc0700000\0" \
 250         "fdtaddr=0xc0600000\0" \
 251         "scriptaddr=0xc0600000\0"
 252
 253 #include <environment/ti/mmc.h>
 254
 255 #define CONFIG_EXTRA_ENV_SETTINGS \
 256         DEFAULT_LINUX_BOOT_ENV \
 257         DEFAULT_MMC_TI_ARGS \
 258         "bootpart=0:2\0" \
 259         "bootdir=/boot\0" \
 260         "bootfile=zImage\0" \
 261         "fdtfile=da850-evm.dtb\0" \
 262         "boot_fdt=yes\0" \
 263         "boot_fit=0\0" \
 264         "console=ttyS2,115200n8\0" \
 265         "hwconfig=dsp:wake=yes"
 266
 267 #ifdef CONFIG_CMD_BDI
 268 #define CONFIG_CLOCKS
 269 #endif
 270
 271 #if !defined(CONFIG_NAND) && \
 272         !defined(CONFIG_USE_NOR) && \
 273         !defined(CONFIG_USE_SPIFLASH)
 274 #define CONFIG_ENV_SIZE         (16 << 10)
 275 #endif
 276
 277 #ifndef CONFIG_DIRECT_NOR_BOOT
 278 /* defines for SPL */
 279 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 280                                                 CONFIG_SYS_MALLOC_LEN)
 281 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 282 #define CONFIG_SPL_STACK        0x8001ff00
 283 #define CONFIG_SPL_TEXT_BASE    0x80000000
 284 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 285 #define CONFIG_SPL_PAD_TO       32768
 286 #endif
 287
 288 /* Load U-Boot Image From MMC */
 289
 290 /* additions for new relocation code, must added to all boards */
 291 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 292
 293 #ifdef CONFIG_DIRECT_NOR_BOOT
 294 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 295 #else
 296 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 297                                         GENERATED_GBL_DATA_SIZE)
 298 #endif /* CONFIG_DIRECT_NOR_BOOT */
 299
 300 #include <asm/arch/hardware.h>
 301
 302 #endif /* __CONFIG_H */