include/configs/da850evm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16 /* check if direct NOR boot config is used */
  17 #ifndef CONFIG_DIRECT_NOR_BOOT
  18 #define CONFIG_USE_SPIFLASH
  19 #endif
  20
  21 /*
  22  * SoC Configuration
  23  */
  24 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  25 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  26 #define CONFIG_SYS_OSCIN_FREQ           24000000
  27 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  28 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  29 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  30
  31 #ifdef CONFIG_DIRECT_NOR_BOOT
  32 #define CONFIG_ARCH_CPU_INIT
  33 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  34 #endif
  35
  36 /*
  37  * Memory Info
  38  */
  39 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  40 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  41 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  42 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  43 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  44 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  45 /* memtest start addr */
  46 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  47
  48 /* memtest will be run on 16MB */
  49 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  50
  51 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  52         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  53         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  54         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  55         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  56         DAVINCI_SYSCFG_SUSPSRC_I2C)
  57
  58 /*
  59  * PLL configuration
  60  */
  61
  62 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  63 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  64
  65 /*
  66  * DDR2 memory configuration
  67  */
  68 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  69                                         DV_DDR_PHY_EXT_STRBEN | \
  70                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  71
  72 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  73         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  74         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  75         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  76         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  77         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  78         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  79         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  80
  81 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  82 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  83
  84 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  85         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  86         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  87         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  88         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  89         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  90         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  91         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  92         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  93
  94 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  95         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  96         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  97         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  98         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  99         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
 100         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
 101         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
 102
 103 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
 104 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 105
 106 /*
 107  * Serial Driver info
 108  */
 109 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 110
 111 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 112
 113 #ifdef CONFIG_USE_SPIFLASH
 114 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
 115 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x40000
 116 #endif
 117
 118 /*
 119  * I2C Configuration
 120  */
 121 #ifndef CONFIG_SPL_BUILD
 122 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 123 #endif
 124
 125 /*
 126  * Flash & Environment
 127  */
 128 #ifdef CONFIG_NAND
 129 #ifdef CONFIG_ENV_IS_IN_NAND
 130 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
 131 #define CONFIG_ENV_SIZE                 (128 << 10)
 132 #define CONFIG_ENV_SECT_SIZE    (128 << 10)
 133 #endif
 134 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 135 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 136 #define CONFIG_SYS_NAND_PAGE_2K
 137 #define CONFIG_SYS_NAND_CS              3
 138 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 139 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 140 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 141 #undef CONFIG_SYS_NAND_HW_ECC
 142 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 143 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 144 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 145 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 146 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 147 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x40000
 148 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 149 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 150 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 151                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 152                                         CONFIG_SYS_MALLOC_LEN -       \
 153                                         GENERATED_GBL_DATA_SIZE)
 154 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 155                                 24, 25, 26, 27, 28, \
 156                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 157                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 158                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 159                                 59, 60, 61, 62, 63 }
 160 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 161 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 162 #define CONFIG_SYS_NAND_ECCSIZE         512
 163 #define CONFIG_SYS_NAND_ECCBYTES        10
 164 #define CONFIG_SYS_NAND_OOBSIZE         64
 165 #define CONFIG_SPL_NAND_BASE
 166 #define CONFIG_SPL_NAND_DRIVERS
 167 #define CONFIG_SPL_NAND_ECC
 168 #define CONFIG_SPL_NAND_LOAD
 169
 170 #ifndef CONFIG_SPL_BUILD
 171 #define CONFIG_SYS_NAND_SELF_INIT
 172 #endif
 173 #endif
 174
 175 /*
 176  * Network & Ethernet Configuration
 177  */
 178 #ifdef CONFIG_DRIVER_TI_EMAC
 179 #define CONFIG_BOOTP_DNS2
 180 #define CONFIG_BOOTP_SEND_HOSTNAME
 181 #define CONFIG_NET_RETRY_COUNT  10
 182 #endif
 183
 184 #ifdef CONFIG_USE_NOR
 185 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 186 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 187 #define CONFIG_ENV_OFFSET               (SZ_1M)
 188 #define CONFIG_ENV_SIZE                 (10 << 10) /* 10KB */
 189 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 190 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 191 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 192                + 3)
 193 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
 194 #endif
 195
 196 #ifdef CONFIG_USE_SPIFLASH
 197 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 198 #define CONFIG_ENV_SIZE                 (64 << 10)
 199 #define CONFIG_ENV_OFFSET               (512 << 10)
 200 #define CONFIG_ENV_SECT_SIZE    (64 << 10)
 201 #endif
 202 #ifdef CONFIG_SPL_BUILD
 203 #undef CONFIG_SPI_FLASH_MTD
 204 #endif
 205 #endif
 206
 207 /*
 208  * U-Boot general configuration
 209  */
 210 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 211 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 212 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 213 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 214 #define CONFIG_MX_CYCLIC
 215
 216 /*
 217  * Linux Information
 218  */
 219 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 220 #define CONFIG_HWCONFIG         /* enable hwconfig */
 221 #define CONFIG_CMDLINE_TAG
 222 #define CONFIG_REVISION_TAG
 223 #define CONFIG_SETUP_MEMORY_TAGS
 224
 225 #define CONFIG_BOOTCOMMAND \
 226                 "run envboot; " \
 227                 "run mmcboot; "
 228
 229 #define DEFAULT_LINUX_BOOT_ENV \
 230         "loadaddr=0xc0700000\0" \
 231         "fdtaddr=0xc0600000\0" \
 232         "scriptaddr=0xc0600000\0"
 233
 234 #include <environment/ti/mmc.h>
 235
 236 #define CONFIG_EXTRA_ENV_SETTINGS \
 237         DEFAULT_LINUX_BOOT_ENV \
 238         DEFAULT_MMC_TI_ARGS \
 239         "bootpart=0:2\0" \
 240         "bootdir=/boot\0" \
 241         "bootfile=zImage\0" \
 242         "fdtfile=da850-evm.dtb\0" \
 243         "boot_fdt=yes\0" \
 244         "boot_fit=0\0" \
 245         "console=ttyS2,115200n8\0" \
 246         "hwconfig=dsp:wake=yes"
 247
 248 #ifdef CONFIG_CMD_BDI
 249 #define CONFIG_CLOCKS
 250 #endif
 251
 252 #if !defined(CONFIG_NAND) && \
 253         !defined(CONFIG_USE_NOR) && \
 254         !defined(CONFIG_USE_SPIFLASH)
 255 #define CONFIG_ENV_SIZE         (16 << 10)
 256 #endif
 257
 258 /* USB Configs */
 259 #define CONFIG_USB_OHCI_NEW
 260 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 261
 262 #ifndef CONFIG_DIRECT_NOR_BOOT
 263 /* defines for SPL */
 264 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 265                                                 CONFIG_SYS_MALLOC_LEN)
 266 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 267 #define CONFIG_SPL_STACK        0x8001ff00
 268 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 269 #define CONFIG_SPL_PAD_TO       32768
 270 #endif
 271
 272 /* Load U-Boot Image From MMC */
 273
 274 /* additions for new relocation code, must added to all boards */
 275 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 276
 277 #ifdef CONFIG_DIRECT_NOR_BOOT
 278 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 279 #else
 280 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 281                                         GENERATED_GBL_DATA_SIZE)
 282 #endif /* CONFIG_DIRECT_NOR_BOOT */
 283
 284 #include <asm/arch/hardware.h>
 285
 286 #endif /* __CONFIG_H */