include/configs/da850evm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16
  17 /*
  18  * SoC Configuration
  19  */
  20 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  21 #define CONFIG_SYS_OSCIN_FREQ           24000000
  22 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  23 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  24
  25 #ifdef CONFIG_MTD_NOR_FLASH
  26 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  27 #endif
  28
  29 /*
  30  * Memory Info
  31  */
  32 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  33 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  34 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  35 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  36 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  37 /* memtest start addr */
  38
  39 /* memtest will be run on 16MB */
  40
  41 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  42         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  43         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  44         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  45         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  46         DAVINCI_SYSCFG_SUSPSRC_I2C)
  47
  48 /*
  49  * PLL configuration
  50  */
  51
  52 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  53 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  54
  55 /*
  56  * DDR2 memory configuration
  57  */
  58 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  59                                         DV_DDR_PHY_EXT_STRBEN | \
  60                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  61
  62 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  63         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  64         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  65         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  66         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  67         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  68         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  69         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  70
  71 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  72 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  73
  74 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  75         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  76         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  77         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  78         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  79         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  80         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  81         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  82         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  83
  84 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  85         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  86         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  87         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  88         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  89         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
  90         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
  91         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
  92
  93 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
  94 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
  95
  96 /*
  97  * Serial Driver info
  98  */
  99 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 100
 101 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 102
 103 /*
 104  * I2C Configuration
 105  */
 106 #ifndef CONFIG_SPL_BUILD
 107 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 108 #endif
 109
 110 /*
 111  * Flash & Environment
 112  */
 113 #ifdef CONFIG_MTD_RAW_NAND
 114 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 115 #define CONFIG_SYS_NAND_PAGE_2K
 116 #define CONFIG_SYS_NAND_CS              3
 117 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 118 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 119 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 120 #undef CONFIG_SYS_NAND_HW_ECC
 121 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 122 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 123 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x40000
 124 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 125 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 126 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 127                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 128                                         CONFIG_SYS_MALLOC_LEN -       \
 129                                         GENERATED_GBL_DATA_SIZE)
 130 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 131                                 24, 25, 26, 27, 28, \
 132                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 133                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 134                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 135                                 59, 60, 61, 62, 63 }
 136 #define CONFIG_SYS_NAND_ECCSIZE         512
 137 #define CONFIG_SYS_NAND_ECCBYTES        10
 138 #endif
 139
 140 #ifdef CONFIG_MTD_NOR_FLASH
 141 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 142 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 143 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 144 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 145                + 3)
 146 #endif
 147
 148 /*
 149  * U-Boot general configuration
 150  */
 151 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 152 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 153
 154 /*
 155  * Linux Information
 156  */
 157 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 158 #define CONFIG_HWCONFIG         /* enable hwconfig */
 159
 160 #define DEFAULT_LINUX_BOOT_ENV \
 161         "loadaddr=0xc0700000\0" \
 162         "fdtaddr=0xc0600000\0" \
 163         "scriptaddr=0xc0600000\0"
 164
 165 #include <environment/ti/mmc.h>
 166
 167 #define CONFIG_EXTRA_ENV_SETTINGS \
 168         DEFAULT_LINUX_BOOT_ENV \
 169         DEFAULT_MMC_TI_ARGS \
 170         "bootpart=0:2\0" \
 171         "bootdir=/boot\0" \
 172         "bootfile=zImage\0" \
 173         "fdtfile=da850-evm.dtb\0" \
 174         "boot_fdt=yes\0" \
 175         "boot_fit=0\0" \
 176         "console=ttyS2,115200n8\0" \
 177         "hwconfig=dsp:wake=yes"
 178
 179 /* USB Configs */
 180 #define CONFIG_USB_OHCI_NEW
 181 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 182
 183 #ifndef CONFIG_MTD_NOR_FLASH
 184 #define CONFIG_SPL_PAD_TO       32768
 185 #endif
 186
 187 #ifdef CONFIG_SPL_BUILD
 188 /* defines for SPL */
 189 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 190                                                 CONFIG_SYS_MALLOC_LEN)
 191 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 192 #define CONFIG_SPL_STACK        0x8001ff00
 193 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 194
 195 #endif
 196
 197 /* Load U-Boot Image From MMC */
 198
 199 /* additions for new relocation code, must added to all boards */
 200 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 201
 202 #ifdef CONFIG_MTD_NOR_FLASH
 203 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 204 #else
 205 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 206                                         GENERATED_GBL_DATA_SIZE)
 207 #endif /* CONFIG_MTD_NOR_FLASH */
 208
 209 #include <asm/arch/hardware.h>
 210
 211 #endif /* __CONFIG_H */