include/configs/da850evm.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on davinci_dvevm.h. Original Copyrights follow:
   6  *
   7  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * Board
  15  */
  16 /* check if direct NOR boot config is used */
  17 #ifndef CONFIG_DIRECT_NOR_BOOT
  18 #define CONFIG_USE_SPIFLASH
  19 #endif
  20
  21 /*
  22  * SoC Configuration
  23  */
  24 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  25 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  26 #define CONFIG_SYS_OSCIN_FREQ           24000000
  27 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  28 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  29 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  30
  31 #ifdef CONFIG_DIRECT_NOR_BOOT
  32 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
  33 #endif
  34
  35 /*
  36  * Memory Info
  37  */
  38 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  39 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  40 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  41 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  42 #define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
  43 #define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
  44 /* memtest start addr */
  45 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  46
  47 /* memtest will be run on 16MB */
  48 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  49
  50 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (       \
  51         DAVINCI_SYSCFG_SUSPSRC_TIMER0 |         \
  52         DAVINCI_SYSCFG_SUSPSRC_SPI1 |           \
  53         DAVINCI_SYSCFG_SUSPSRC_UART2 |          \
  54         DAVINCI_SYSCFG_SUSPSRC_EMAC |           \
  55         DAVINCI_SYSCFG_SUSPSRC_I2C)
  56
  57 /*
  58  * PLL configuration
  59  */
  60
  61 #define CONFIG_SYS_DA850_PLL0_PLLM     24
  62 #define CONFIG_SYS_DA850_PLL1_PLLM     21
  63
  64 /*
  65  * DDR2 memory configuration
  66  */
  67 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
  68                                         DV_DDR_PHY_EXT_STRBEN | \
  69                                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
  70
  71 #define CONFIG_SYS_DA850_DDR2_SDBCR (           \
  72         (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |     \
  73         (1 << DV_DDR_SDCR_DDREN_SHIFT) |        \
  74         (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |      \
  75         (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |    \
  76         (0x3 << DV_DDR_SDCR_CL_SHIFT) |         \
  77         (0x2 << DV_DDR_SDCR_IBANK_SHIFT) |      \
  78         (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
  79
  80 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
  81 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0
  82
  83 #define CONFIG_SYS_DA850_DDR2_SDTIMR (          \
  84         (14 << DV_DDR_SDTMR1_RFC_SHIFT) |       \
  85         (2 << DV_DDR_SDTMR1_RP_SHIFT) |         \
  86         (2 << DV_DDR_SDTMR1_RCD_SHIFT) |        \
  87         (1 << DV_DDR_SDTMR1_WR_SHIFT) |         \
  88         (5 << DV_DDR_SDTMR1_RAS_SHIFT) |        \
  89         (8 << DV_DDR_SDTMR1_RC_SHIFT) |         \
  90         (1 << DV_DDR_SDTMR1_RRD_SHIFT) |        \
  91         (0 << DV_DDR_SDTMR1_WTR_SHIFT))
  92
  93 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (         \
  94         (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |     \
  95         (0 << DV_DDR_SDTMR2_XP_SHIFT) |         \
  96         (0 << DV_DDR_SDTMR2_ODT_SHIFT) |        \
  97         (17 << DV_DDR_SDTMR2_XSNR_SHIFT) |      \
  98         (199 << DV_DDR_SDTMR2_XSRD_SHIFT) |     \
  99         (0 << DV_DDR_SDTMR2_RTP_SHIFT) |        \
 100         (0 << DV_DDR_SDTMR2_CKE_SHIFT))
 101
 102 #define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
 103 #define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
 104
 105 /*
 106  * Serial Driver info
 107  */
 108 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
 109
 110 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
 111
 112 #ifdef CONFIG_USE_SPIFLASH
 113 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x8000
 114 #define CONFIG_SYS_SPI_U_BOOT_SIZE      0x40000
 115 #endif
 116
 117 /*
 118  * I2C Configuration
 119  */
 120 #ifndef CONFIG_SPL_BUILD
 121 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 122 #endif
 123
 124 /*
 125  * Flash & Environment
 126  */
 127 #ifdef CONFIG_NAND
 128 #ifdef CONFIG_ENV_IS_IN_NAND
 129 #define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
 130 #define CONFIG_ENV_SIZE                 (128 << 10)
 131 #define CONFIG_ENV_SECT_SIZE    (128 << 10)
 132 #endif
 133 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 134 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 135 #define CONFIG_SYS_NAND_PAGE_2K
 136 #define CONFIG_SYS_NAND_CS              3
 137 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 138 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 139 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 140 #undef CONFIG_SYS_NAND_HW_ECC
 141 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 142 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
 143 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 144 #define CONFIG_SYS_NAND_PAGE_SIZE       (2 << 10)
 145 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
 146 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x40000
 147 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc1080000
 148 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 149 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
 150                                         CONFIG_SYS_NAND_U_BOOT_SIZE - \
 151                                         CONFIG_SYS_MALLOC_LEN -       \
 152                                         GENERATED_GBL_DATA_SIZE)
 153 #define CONFIG_SYS_NAND_ECCPOS          {                               \
 154                                 24, 25, 26, 27, 28, \
 155                                 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
 156                                 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
 157                                 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
 158                                 59, 60, 61, 62, 63 }
 159 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 160 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 161 #define CONFIG_SYS_NAND_ECCSIZE         512
 162 #define CONFIG_SYS_NAND_ECCBYTES        10
 163 #define CONFIG_SYS_NAND_OOBSIZE         64
 164 #define CONFIG_SPL_NAND_BASE
 165 #define CONFIG_SPL_NAND_DRIVERS
 166 #define CONFIG_SPL_NAND_ECC
 167 #define CONFIG_SPL_NAND_LOAD
 168
 169 #ifndef CONFIG_SPL_BUILD
 170 #define CONFIG_SYS_NAND_SELF_INIT
 171 #endif
 172 #endif
 173
 174 /*
 175  * Network & Ethernet Configuration
 176  */
 177 #ifdef CONFIG_DRIVER_TI_EMAC
 178 #define CONFIG_BOOTP_DNS2
 179 #define CONFIG_BOOTP_SEND_HOSTNAME
 180 #define CONFIG_NET_RETRY_COUNT  10
 181 #endif
 182
 183 #ifdef CONFIG_USE_NOR
 184 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* max number of flash banks */
 185 #define CONFIG_SYS_FLASH_SECT_SZ        (128 << 10) /* 128KB */
 186 #define CONFIG_ENV_OFFSET               (SZ_1M)
 187 #define CONFIG_ENV_SIZE                 (10 << 10) /* 10KB */
 188 #define CONFIG_SYS_FLASH_BASE           DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
 189 #define PHYS_FLASH_SIZE                 (8 << 20) /* Flash size 8MB */
 190 #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
 191                + 3)
 192 #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_FLASH_SECT_SZ
 193 #endif
 194
 195 #ifdef CONFIG_USE_SPIFLASH
 196 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 197 #define CONFIG_ENV_SIZE                 (64 << 10)
 198 #define CONFIG_ENV_OFFSET               (512 << 10)
 199 #define CONFIG_ENV_SECT_SIZE    (64 << 10)
 200 #endif
 201 #ifdef CONFIG_SPL_BUILD
 202 #undef CONFIG_SPI_FLASH_MTD
 203 #endif
 204 #endif
 205
 206 /*
 207  * U-Boot general configuration
 208  */
 209 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 210 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 211 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 212 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 213
 214 /*
 215  * Linux Information
 216  */
 217 #define LINUX_BOOT_PARAM_ADDR   (PHYS_SDRAM_1 + 0x100)
 218 #define CONFIG_HWCONFIG         /* enable hwconfig */
 219 #define CONFIG_CMDLINE_TAG
 220 #define CONFIG_REVISION_TAG
 221 #define CONFIG_SETUP_MEMORY_TAGS
 222
 223 #define CONFIG_BOOTCOMMAND \
 224                 "run envboot; " \
 225                 "run mmcboot; "
 226
 227 #define DEFAULT_LINUX_BOOT_ENV \
 228         "loadaddr=0xc0700000\0" \
 229         "fdtaddr=0xc0600000\0" \
 230         "scriptaddr=0xc0600000\0"
 231
 232 #include <environment/ti/mmc.h>
 233
 234 #define CONFIG_EXTRA_ENV_SETTINGS \
 235         DEFAULT_LINUX_BOOT_ENV \
 236         DEFAULT_MMC_TI_ARGS \
 237         "bootpart=0:2\0" \
 238         "bootdir=/boot\0" \
 239         "bootfile=zImage\0" \
 240         "fdtfile=da850-evm.dtb\0" \
 241         "boot_fdt=yes\0" \
 242         "boot_fit=0\0" \
 243         "console=ttyS2,115200n8\0" \
 244         "hwconfig=dsp:wake=yes"
 245
 246 #ifdef CONFIG_CMD_BDI
 247 #define CONFIG_CLOCKS
 248 #endif
 249
 250 #if !defined(CONFIG_NAND) && \
 251         !defined(CONFIG_USE_NOR) && \
 252         !defined(CONFIG_USE_SPIFLASH)
 253 #define CONFIG_ENV_SIZE         (16 << 10)
 254 #endif
 255
 256 /* USB Configs */
 257 #define CONFIG_USB_OHCI_NEW
 258 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 259
 260 #ifndef CONFIG_DIRECT_NOR_BOOT
 261 /* defines for SPL */
 262 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 263                                                 CONFIG_SYS_MALLOC_LEN)
 264 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 265 #define CONFIG_SPL_STACK        0x8001ff00
 266 #define CONFIG_SPL_MAX_FOOTPRINT        32768
 267 #define CONFIG_SPL_PAD_TO       32768
 268 #endif
 269
 270 /* Load U-Boot Image From MMC */
 271
 272 /* additions for new relocation code, must added to all boards */
 273 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 274
 275 #ifdef CONFIG_DIRECT_NOR_BOOT
 276 #define CONFIG_SYS_INIT_SP_ADDR         0x8001ff00
 277 #else
 278 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
 279                                         GENERATED_GBL_DATA_SIZE)
 280 #endif /* CONFIG_DIRECT_NOR_BOOT */
 281
 282 #include <asm/arch/hardware.h>
 283
 284 #endif /* __CONFIG_H */