1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Based on corenet_ds.h
9 #include <linux/stringify.h>
11 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
12 #error Must call Cyrus CONFIG with a specific CPU enabled.
16 #define CONFIG_FSL_SATA_V2
19 #ifdef CONFIG_ARCH_P5020
20 #define CONFIG_SYS_FSL_RAID_ENGINE
21 #define CONFIG_SYS_DPAA_RMAN
23 #define CONFIG_SYS_DPAA_PME
26 * Corenet DS style board configuration file
28 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
29 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
30 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
31 #if defined(CONFIG_ARCH_P5020)
32 #define CONFIG_SYS_CLK_FREQ 133000000
33 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
34 #elif defined(CONFIG_ARCH_P5040)
35 #define CONFIG_SYS_CLK_FREQ 100000000
36 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
39 /* High Level Configuration Options */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
42 #define CONFIG_SYS_MMC_MAX_DEVICE 1
44 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
45 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
46 #define CONFIG_PCIE1 /* PCIE controller 1 */
47 #define CONFIG_PCIE2 /* PCIE controller 2 */
48 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
49 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
51 #if defined(CONFIG_SDCARD)
52 #define CONFIG_FSL_FIXED_MMC_LOCATION
53 #define CONFIG_SYS_MMC_ENV_DEV 0
57 * These can be toggled for performance analysis, otherwise use default.
59 #define CONFIG_SYS_CACHE_STASHING
60 #define CONFIG_BACKSIDE_L2_CACHE
61 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
62 #define CONFIG_BTB /* toggle branch predition */
63 #define CONFIG_DDR_ECC
65 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
66 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
69 #define CONFIG_ENABLE_36BIT_PHYS
71 /* test POST memory test */
75 * Config the L3 Cache as L3 SRAM
77 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
78 #ifdef CONFIG_PHYS_64BIT
79 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
81 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
83 #define CONFIG_SYS_L3_SIZE (1024 << 10)
84 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
86 #ifdef CONFIG_PHYS_64BIT
87 #define CONFIG_SYS_DCSRBAR 0xf0000000
88 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
94 #define CONFIG_VERY_BIG_RAM
95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
99 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
101 #define CONFIG_DDR_SPD
103 #define CONFIG_SYS_SPD_BUS_NUM 1
104 #define SPD_EEPROM_ADDRESS1 0x51
105 #define SPD_EEPROM_ADDRESS2 0x52
106 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
109 * Local Bus Definitions
112 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
113 #ifdef CONFIG_PHYS_64BIT
114 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
116 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
119 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
120 #ifdef CONFIG_PHYS_64BIT
121 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
123 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
126 /* Set the local bus clock 1/16 of platform clock */
127 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
129 #define CONFIG_SYS_BR0_PRELIM \
130 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
131 #define CONFIG_SYS_BR1_PRELIM \
132 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
134 #define CONFIG_SYS_OR0_PRELIM 0xfff00010
135 #define CONFIG_SYS_OR1_PRELIM 0xfff00010
137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
139 #if defined(CONFIG_RAMBOOT_PBL)
140 #define CONFIG_SYS_RAMBOOT
143 #define CONFIG_HWCONFIG
145 /* define to use L1 as initial stack */
146 #define CONFIG_L1_INIT_RAM
147 #define CONFIG_SYS_INIT_RAM_LOCK
148 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
149 #ifdef CONFIG_PHYS_64BIT
150 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
151 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
152 /* The assembler doesn't like typecast */
153 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
154 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
155 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
157 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
161 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
163 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
164 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
166 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
167 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
169 /* Serial Port - controlled on board with jumper J8
173 #define CONFIG_SYS_NS16550_SERIAL
174 #define CONFIG_SYS_NS16550_REG_SIZE 1
175 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
177 #define CONFIG_SYS_BAUDRATE_TABLE \
178 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
180 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
181 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
182 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
183 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
186 #define CONFIG_SYS_I2C
187 #define CONFIG_SYS_I2C_FSL
188 #define CONFIG_I2C_MULTI_BUS
189 #define CONFIG_I2C_CMD_TREE
190 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
191 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
192 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
193 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
194 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
195 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
196 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
197 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
198 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
199 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
200 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
201 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
203 #define CONFIG_ID_EEPROM
204 #define CONFIG_SYS_I2C_EEPROM_NXID
205 #define CONFIG_SYS_EEPROM_BUS_NUM 0
206 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
207 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
209 #define CONFIG_SYS_I2C_GENERIC_MAC
210 #define CONFIG_SYS_I2C_MAC1_BUS 3
211 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
212 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
213 #define CONFIG_SYS_I2C_MAC2_BUS 0
214 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
215 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
217 #define CONFIG_RTC_MCP79411 1
218 #define CONFIG_SYS_RTC_BUS_NUM 3
219 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f
222 * eSPI - Enhanced SPI
227 * Memory space is mapped 1-1, but I/O space must start from 0.
230 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
231 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
232 #ifdef CONFIG_PHYS_64BIT
233 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
234 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
236 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
237 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
239 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
240 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
241 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
242 #ifdef CONFIG_PHYS_64BIT
243 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
245 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
247 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
249 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
250 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
251 #ifdef CONFIG_PHYS_64BIT
252 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
253 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
255 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
256 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
258 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
259 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
260 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
261 #ifdef CONFIG_PHYS_64BIT
262 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
264 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
266 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
268 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
269 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
270 #ifdef CONFIG_PHYS_64BIT
271 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
272 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
274 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
275 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
277 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
278 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
279 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
280 #ifdef CONFIG_PHYS_64BIT
281 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
283 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
285 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
287 /* controller 4, Base address 203000 */
288 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
289 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
290 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
291 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
292 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
293 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
296 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
297 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
298 #ifdef CONFIG_PHYS_64BIT
299 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
301 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
303 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
304 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
305 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
306 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
307 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
308 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
309 CONFIG_SYS_BMAN_CENA_SIZE)
310 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
311 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
312 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
313 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
314 #ifdef CONFIG_PHYS_64BIT
315 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
317 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
319 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
320 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
321 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
322 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
323 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
324 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
325 CONFIG_SYS_QMAN_CENA_SIZE)
326 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
327 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
329 #define CONFIG_SYS_DPAA_FMAN
330 /* Default address of microcode for the Linux Fman driver */
332 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
333 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
334 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
336 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
338 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
339 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
342 #define CONFIG_PCI_INDIRECT_BRIDGE
344 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
345 #endif /* CONFIG_PCI */
348 #ifdef CONFIG_FSL_SATA_V2
349 #define CONFIG_SYS_SATA_MAX_DEVICE 2
351 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
352 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
354 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
355 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
360 #ifdef CONFIG_FMAN_ENET
361 #define CONFIG_SYS_TBIPA_VALUE 8
362 #define CONFIG_ETHPRIME "FM1@DTSEC4"
368 #define CONFIG_LOADS_ECHO /* echo on for serial download */
369 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
374 #define CONFIG_HAS_FSL_DR_USB
375 #define CONFIG_HAS_FSL_MPH_USB
377 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
378 #define CONFIG_USB_EHCI_FSL
379 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
380 #define CONFIG_EHCI_IS_TDI
381 /* _VIA_CONTROL_EP */
385 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
386 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
390 * Miscellaneous configurable options
392 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
395 * For booting Linux, the board info and command line data
396 * have to be in the first 64 MB of memory, since this is
397 * the maximum mapped by the Linux kernel during initialization.
399 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
400 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
402 #ifdef CONFIG_CMD_KGDB
403 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
407 * Environment Configuration
409 #define CONFIG_ROOTPATH "/opt/nfsroot"
410 #define CONFIG_BOOTFILE "uImage"
411 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
413 /* default location for tftp and bootm */
414 #define CONFIG_LOADADDR 1000000
416 #define __USB_PHY_TYPE utmi
418 #define CONFIG_EXTRA_ENV_SETTINGS \
419 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
420 "bank_intlv=cs0_cs1;" \
421 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
422 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
424 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
425 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
426 "consoledev=ttyS0\0" \
427 "ramdiskaddr=2000000\0" \
428 "fdtaddr=1e00000\0" \
431 #define CONFIG_HDBOOT \
432 "setenv bootargs root=/dev/$bdev rw " \
433 "console=$consoledev,$baudrate $othbootargs;" \
434 "tftp $loadaddr $bootfile;" \
435 "tftp $fdtaddr $fdtfile;" \
436 "bootm $loadaddr - $fdtaddr"
438 #define CONFIG_NFSBOOTCOMMAND \
439 "setenv bootargs root=/dev/nfs rw " \
440 "nfsroot=$serverip:$rootpath " \
441 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
442 "console=$consoledev,$baudrate $othbootargs;" \
443 "tftp $loadaddr $bootfile;" \
444 "tftp $fdtaddr $fdtfile;" \
445 "bootm $loadaddr - $fdtaddr"
447 #define CONFIG_RAMBOOTCOMMAND \
448 "setenv bootargs root=/dev/ram rw " \
449 "console=$consoledev,$baudrate $othbootargs;" \
450 "tftp $ramdiskaddr $ramdiskfile;" \
451 "tftp $loadaddr $bootfile;" \
452 "tftp $fdtaddr $fdtfile;" \
453 "bootm $loadaddr $ramdiskaddr $fdtaddr"
455 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
457 #include <asm/fsl_secure_boot.h>
459 #endif /* __CONFIG_H */