include/configs/cyrus.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Based on corenet_ds.h
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 #include <linux/stringify.h>
  10
  11 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
  12 #error Must call Cyrus CONFIG with a specific CPU enabled.
  13 #endif
  14
  15 #define CONFIG_SDCARD
  16 #define CONFIG_FSL_SATA_V2
  17 #define CONFIG_PCIE3
  18 #define CONFIG_PCIE4
  19 #ifdef CONFIG_ARCH_P5020
  20 #define CONFIG_SYS_FSL_RAID_ENGINE
  21 #define CONFIG_SYS_DPAA_RMAN
  22 #endif
  23 #define CONFIG_SYS_DPAA_PME
  24
  25 /*
  26  * Corenet DS style board configuration file
  27  */
  28 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  29 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  30 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
  31 #if defined(CONFIG_ARCH_P5020)
  32 #define CONFIG_SYS_CLK_FREQ 133000000
  33 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
  34 #elif defined(CONFIG_ARCH_P5040)
  35 #define CONFIG_SYS_CLK_FREQ 100000000
  36 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
  37 #endif
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  41
  42 #define CONFIG_SYS_MMC_MAX_DEVICE     1
  43
  44 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  45 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  46 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  47 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  48 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  49 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  50
  51 #if defined(CONFIG_SDCARD)
  52 #define CONFIG_FSL_FIXED_MMC_LOCATION
  53 #endif
  54
  55 /*
  56  * These can be toggled for performance analysis, otherwise use default.
  57  */
  58 #define CONFIG_SYS_CACHE_STASHING
  59 #define CONFIG_BACKSIDE_L2_CACHE
  60 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  61 #define CONFIG_BTB                      /* toggle branch predition */
  62 #define CONFIG_DDR_ECC
  63 #ifdef CONFIG_DDR_ECC
  64 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  65 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  66 #endif
  67
  68 #define CONFIG_ENABLE_36BIT_PHYS
  69
  70 /* test POST memory test */
  71 #undef CONFIG_POST
  72
  73 /*
  74  *  Config the L3 Cache as L3 SRAM
  75  */
  76 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  77 #ifdef CONFIG_PHYS_64BIT
  78 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  79 #else
  80 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  81 #endif
  82 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  83 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  84
  85 #ifdef CONFIG_PHYS_64BIT
  86 #define CONFIG_SYS_DCSRBAR              0xf0000000
  87 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  88 #endif
  89
  90 /*
  91  * DDR Setup
  92  */
  93 #define CONFIG_VERY_BIG_RAM
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  95 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  96
  97 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  98 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  99
 100 #define CONFIG_DDR_SPD
 101
 102 #define CONFIG_SYS_SPD_BUS_NUM  1
 103 #define SPD_EEPROM_ADDRESS1     0x51
 104 #define SPD_EEPROM_ADDRESS2     0x52
 105 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 106
 107 /*
 108  * Local Bus Definitions
 109  */
 110
 111 #define CONFIG_SYS_LBC0_BASE            0xe0000000 /* Start of LBC Registers */
 112 #ifdef CONFIG_PHYS_64BIT
 113 #define CONFIG_SYS_LBC0_BASE_PHYS       0xfe0000000ull
 114 #else
 115 #define CONFIG_SYS_LBC0_BASE_PHYS       CONFIG_SYS_LBC0_BASE
 116 #endif
 117
 118 #define CONFIG_SYS_LBC1_BASE            0xe1000000 /* Start of LBC Registers */
 119 #ifdef CONFIG_PHYS_64BIT
 120 #define CONFIG_SYS_LBC1_BASE_PHYS       0xfe1000000ull
 121 #else
 122 #define CONFIG_SYS_LBC1_BASE_PHYS       CONFIG_SYS_LBC1_BASE
 123 #endif
 124
 125 /* Set the local bus clock 1/16 of platform clock */
 126 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_16 | LCRR_EADC_1)
 127
 128 #define CONFIG_SYS_BR0_PRELIM \
 129 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
 130 #define CONFIG_SYS_BR1_PRELIM \
 131 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
 132
 133 #define CONFIG_SYS_OR0_PRELIM   0xfff00010
 134 #define CONFIG_SYS_OR1_PRELIM   0xfff00010
 135
 136 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 137
 138 #if defined(CONFIG_RAMBOOT_PBL)
 139 #define CONFIG_SYS_RAMBOOT
 140 #endif
 141
 142 #define CONFIG_HWCONFIG
 143
 144 /* define to use L1 as initial stack */
 145 #define CONFIG_L1_INIT_RAM
 146 #define CONFIG_SYS_INIT_RAM_LOCK
 147 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 148 #ifdef CONFIG_PHYS_64BIT
 149 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 150 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 151 /* The assembler doesn't like typecast */
 152 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 153         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 154           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 155 #else
 156 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 157 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 159 #endif
 160 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 161
 162 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 163 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 164
 165 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 166 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 167
 168 /* Serial Port - controlled on board with jumper J8
 169  * open - index 2
 170  * shorted - index 1
 171  */
 172 #define CONFIG_SYS_NS16550_SERIAL
 173 #define CONFIG_SYS_NS16550_REG_SIZE     1
 174 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 175
 176 #define CONFIG_SYS_BAUDRATE_TABLE       \
 177 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 178
 179 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 180 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 181 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 182 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 183
 184 /* I2C */
 185 #define CONFIG_SYS_I2C
 186 #define CONFIG_SYS_I2C_FSL
 187 #define CONFIG_I2C_MULTI_BUS
 188 #define CONFIG_I2C_CMD_TREE
 189 #define CONFIG_SYS_FSL_I2C_SPEED                400000  /* I2C speed and slave address */
 190 #define CONFIG_SYS_FSL_I2C_SLAVE                0x7F
 191 #define CONFIG_SYS_FSL_I2C_OFFSET               0x118000
 192 #define CONFIG_SYS_FSL_I2C2_SPEED               400000  /* I2C speed and slave address */
 193 #define CONFIG_SYS_FSL_I2C2_SLAVE               0x7F
 194 #define CONFIG_SYS_FSL_I2C2_OFFSET              0x118100
 195 #define CONFIG_SYS_FSL_I2C3_SPEED               400000  /* I2C speed and slave address */
 196 #define CONFIG_SYS_FSL_I2C3_SLAVE               0x7F
 197 #define CONFIG_SYS_FSL_I2C3_OFFSET              0x119000
 198 #define CONFIG_SYS_FSL_I2C4_SPEED               400000  /* I2C speed and slave address */
 199 #define CONFIG_SYS_FSL_I2C4_SLAVE               0x7F
 200 #define CONFIG_SYS_FSL_I2C4_OFFSET              0x119100
 201
 202 #define CONFIG_ID_EEPROM
 203 #define CONFIG_SYS_I2C_EEPROM_NXID
 204 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 205 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 206 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 207
 208 #define CONFIG_SYS_I2C_GENERIC_MAC
 209 #define CONFIG_SYS_I2C_MAC1_BUS 3
 210 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
 211 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
 212 #define CONFIG_SYS_I2C_MAC2_BUS 0
 213 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
 214 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
 215
 216 #define CONFIG_RTC_MCP79411             1
 217 #define CONFIG_SYS_RTC_BUS_NUM          3
 218 #define CONFIG_SYS_I2C_RTC_ADDR         0x6f
 219
 220 /*
 221  * eSPI - Enhanced SPI
 222  */
 223
 224 /*
 225  * General PCI
 226  * Memory space is mapped 1-1, but I/O space must start from 0.
 227  */
 228
 229 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 230 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 231 #ifdef CONFIG_PHYS_64BIT
 232 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 233 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 234 #else
 235 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 236 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 237 #endif
 238 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 239 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 240 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 241 #ifdef CONFIG_PHYS_64BIT
 242 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 243 #else
 244 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 245 #endif
 246 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 247
 248 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 249 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 250 #ifdef CONFIG_PHYS_64BIT
 251 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 252 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 253 #else
 254 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 255 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 256 #endif
 257 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 258 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 259 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 260 #ifdef CONFIG_PHYS_64BIT
 261 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 262 #else
 263 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 264 #endif
 265 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 266
 267 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 268 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 269 #ifdef CONFIG_PHYS_64BIT
 270 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 271 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 272 #else
 273 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 274 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 275 #endif
 276 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 277 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 278 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 279 #ifdef CONFIG_PHYS_64BIT
 280 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 281 #else
 282 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 283 #endif
 284 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 285
 286 /* controller 4, Base address 203000 */
 287 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 288 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 289 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 290 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 291 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 292 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 293
 294 /* Qman/Bman */
 295 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 296 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 297 #ifdef CONFIG_PHYS_64BIT
 298 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 299 #else
 300 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 301 #endif
 302 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 303 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 304 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 305 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 306 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 307 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 308                                          CONFIG_SYS_BMAN_CENA_SIZE)
 309 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 310 #define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
 311 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 312 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 313 #ifdef CONFIG_PHYS_64BIT
 314 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 315 #else
 316 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 317 #endif
 318 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 319 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 320 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 321 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 322 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 323 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 324                                           CONFIG_SYS_QMAN_CENA_SIZE)
 325 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 326 #define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
 327
 328 #define CONFIG_SYS_DPAA_FMAN
 329 /* Default address of microcode for the Linux Fman driver */
 330 /*
 331  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 332  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 333  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 334  */
 335 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 336
 337 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 338 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 339
 340 #ifdef CONFIG_PCI
 341 #define CONFIG_PCI_INDIRECT_BRIDGE
 342
 343 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 344 #endif  /* CONFIG_PCI */
 345
 346 /* SATA */
 347 #ifdef CONFIG_FSL_SATA_V2
 348 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 349 #define CONFIG_SATA1
 350 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 351 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 352 #define CONFIG_SATA2
 353 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 354 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 355
 356 #define CONFIG_LBA48
 357 #endif
 358
 359 #ifdef CONFIG_FMAN_ENET
 360 #define CONFIG_SYS_TBIPA_VALUE  8
 361 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 362 #endif
 363
 364 /*
 365  * Environment
 366  */
 367 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 368 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 369
 370 /*
 371  * USB
 372  */
 373 #define CONFIG_HAS_FSL_DR_USB
 374 #define CONFIG_HAS_FSL_MPH_USB
 375
 376 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 377 #define CONFIG_USB_EHCI_FSL
 378 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 379 #define CONFIG_EHCI_IS_TDI
 380  /* _VIA_CONTROL_EP  */
 381 #endif
 382
 383 #ifdef CONFIG_MMC
 384 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 385 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 386 #endif
 387
 388 /*
 389  * Miscellaneous configurable options
 390  */
 391 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 392
 393 /*
 394  * For booting Linux, the board info and command line data
 395  * have to be in the first 64 MB of memory, since this is
 396  * the maximum mapped by the Linux kernel during initialization.
 397  */
 398 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 399 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 400
 401 #ifdef CONFIG_CMD_KGDB
 402 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 403 #endif
 404
 405 /*
 406  * Environment Configuration
 407  */
 408 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 409 #define CONFIG_BOOTFILE         "uImage"
 410 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 411
 412 /* default location for tftp and bootm */
 413 #define CONFIG_LOADADDR         1000000
 414
 415 #define __USB_PHY_TYPE  utmi
 416
 417 #define CONFIG_EXTRA_ENV_SETTINGS \
 418 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 419 "bank_intlv=cs0_cs1;"                                   \
 420 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 421 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 422 "netdev=eth0\0"                                         \
 423 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 424 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 425 "consoledev=ttyS0\0"                                    \
 426 "ramdiskaddr=2000000\0"                                 \
 427 "fdtaddr=1e00000\0"                                     \
 428 "bdev=sda3\0"
 429
 430 #define CONFIG_HDBOOT                                   \
 431 "setenv bootargs root=/dev/$bdev rw "           \
 432 "console=$consoledev,$baudrate $othbootargs;"   \
 433 "tftp $loadaddr $bootfile;"                     \
 434 "tftp $fdtaddr $fdtfile;"                       \
 435 "bootm $loadaddr - $fdtaddr"
 436
 437 #define CONFIG_NFSBOOTCOMMAND                   \
 438 "setenv bootargs root=/dev/nfs rw "     \
 439 "nfsroot=$serverip:$rootpath "          \
 440 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 441 "console=$consoledev,$baudrate $othbootargs;"   \
 442 "tftp $loadaddr $bootfile;"             \
 443 "tftp $fdtaddr $fdtfile;"               \
 444 "bootm $loadaddr - $fdtaddr"
 445
 446 #define CONFIG_RAMBOOTCOMMAND                           \
 447 "setenv bootargs root=/dev/ram rw "             \
 448 "console=$consoledev,$baudrate $othbootargs;"   \
 449 "tftp $ramdiskaddr $ramdiskfile;"               \
 450 "tftp $loadaddr $bootfile;"                     \
 451 "tftp $fdtaddr $fdtfile;"                       \
 452 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 453
 454 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 455
 456 #include <asm/fsl_secure_boot.h>
 457
 458 #endif  /* __CONFIG_H */