2 * Based on corenet_ds.h
4 * SPDX-License-Identifier: GPL-2.0+
10 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
11 #error Must call Cyrus CONFIG with a specific CPU enabled.
15 #define CONFIG_FSL_SATA_V2
18 #ifdef CONFIG_ARCH_P5020
19 #define CONFIG_SYS_FSL_RAID_ENGINE
20 #define CONFIG_SYS_DPAA_RMAN
22 #define CONFIG_SYS_DPAA_PME
25 * Corenet DS style board configuration file
27 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
29 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
30 #if defined(CONFIG_ARCH_P5020)
31 #define CONFIG_SYS_CLK_FREQ 133000000
32 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
33 #elif defined(CONFIG_ARCH_P5040)
34 #define CONFIG_SYS_CLK_FREQ 100000000
35 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
38 /* High Level Configuration Options */
39 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
40 #define CONFIG_MP /* support multiple processors */
42 #define CONFIG_SYS_MMC_MAX_DEVICE 1
44 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
45 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
46 #define CONFIG_PCIE1 /* PCIE controller 1 */
47 #define CONFIG_PCIE2 /* PCIE controller 2 */
48 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
49 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
51 #define CONFIG_ENV_OVERWRITE
53 #if defined(CONFIG_SDCARD)
54 #define CONFIG_SYS_EXTRA_ENV_RELOC
55 #define CONFIG_FSL_FIXED_MMC_LOCATION
56 #define CONFIG_SYS_MMC_ENV_DEV 0
57 #define CONFIG_ENV_SIZE 0x2000
58 #define CONFIG_ENV_OFFSET (512 * 1658)
62 * These can be toggled for performance analysis, otherwise use default.
64 #define CONFIG_SYS_CACHE_STASHING
65 #define CONFIG_BACKSIDE_L2_CACHE
66 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
67 #define CONFIG_BTB /* toggle branch predition */
68 #define CONFIG_DDR_ECC
70 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
71 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
74 #define CONFIG_ENABLE_36BIT_PHYS
76 #ifdef CONFIG_PHYS_64BIT
77 #define CONFIG_ADDR_MAP
78 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
81 /* test POST memory test */
83 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
84 #define CONFIG_SYS_MEMTEST_END 0x00400000
87 * Config the L3 Cache as L3 SRAM
89 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
90 #ifdef CONFIG_PHYS_64BIT
91 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
93 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
95 #define CONFIG_SYS_L3_SIZE (1024 << 10)
96 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
98 #ifdef CONFIG_PHYS_64BIT
99 #define CONFIG_SYS_DCSRBAR 0xf0000000
100 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
106 #define CONFIG_VERY_BIG_RAM
107 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
110 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
111 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
113 #define CONFIG_DDR_SPD
115 #define CONFIG_SYS_SPD_BUS_NUM 1
116 #define SPD_EEPROM_ADDRESS1 0x51
117 #define SPD_EEPROM_ADDRESS2 0x52
118 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
121 * Local Bus Definitions
124 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
125 #ifdef CONFIG_PHYS_64BIT
126 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
128 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
131 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
132 #ifdef CONFIG_PHYS_64BIT
133 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
135 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
138 /* Set the local bus clock 1/16 of platform clock */
139 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
141 #define CONFIG_SYS_BR0_PRELIM \
142 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
143 #define CONFIG_SYS_BR1_PRELIM \
144 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
146 #define CONFIG_SYS_OR0_PRELIM 0xfff00010
147 #define CONFIG_SYS_OR1_PRELIM 0xfff00010
149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
151 #if defined(CONFIG_RAMBOOT_PBL)
152 #define CONFIG_SYS_RAMBOOT
155 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
156 #define CONFIG_MISC_INIT_R
158 #define CONFIG_HWCONFIG
160 /* define to use L1 as initial stack */
161 #define CONFIG_L1_INIT_RAM
162 #define CONFIG_SYS_INIT_RAM_LOCK
163 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
164 #ifdef CONFIG_PHYS_64BIT
165 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
166 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
167 /* The assembler doesn't like typecast */
168 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
169 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
170 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
174 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
176 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
178 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
179 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
181 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
182 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
184 /* Serial Port - controlled on board with jumper J8
188 #define CONFIG_SYS_NS16550_SERIAL
189 #define CONFIG_SYS_NS16550_REG_SIZE 1
190 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
192 #define CONFIG_SYS_BAUDRATE_TABLE \
193 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
195 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
196 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
197 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
198 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
201 #define CONFIG_SYS_I2C
202 #define CONFIG_SYS_I2C_FSL
203 #define CONFIG_I2C_MULTI_BUS
204 #define CONFIG_I2C_CMD_TREE
205 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
206 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
207 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
208 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
209 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
210 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
211 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
212 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
213 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
214 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
215 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
216 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
218 #define CONFIG_ID_EEPROM
219 #define CONFIG_SYS_I2C_EEPROM_NXID
220 #define CONFIG_SYS_EEPROM_BUS_NUM 0
221 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
222 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
224 #define CONFIG_SYS_I2C_GENERIC_MAC
225 #define CONFIG_SYS_I2C_MAC1_BUS 3
226 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
227 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
228 #define CONFIG_SYS_I2C_MAC2_BUS 0
229 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
230 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
232 #define CONFIG_RTC_MCP79411 1
233 #define CONFIG_SYS_RTC_BUS_NUM 3
234 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f
237 * eSPI - Enhanced SPI
242 * Memory space is mapped 1-1, but I/O space must start from 0.
245 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
246 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
247 #ifdef CONFIG_PHYS_64BIT
248 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
249 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
251 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
252 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
254 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
255 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
256 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
257 #ifdef CONFIG_PHYS_64BIT
258 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
260 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
262 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
264 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
265 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
266 #ifdef CONFIG_PHYS_64BIT
267 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
268 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
270 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
271 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
273 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
274 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
275 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
276 #ifdef CONFIG_PHYS_64BIT
277 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
279 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
281 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
283 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
284 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
285 #ifdef CONFIG_PHYS_64BIT
286 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
287 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
289 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
290 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
292 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
293 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
294 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
295 #ifdef CONFIG_PHYS_64BIT
296 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
298 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
300 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
302 /* controller 4, Base address 203000 */
303 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
304 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
305 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
306 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
307 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
308 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
311 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
312 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
313 #ifdef CONFIG_PHYS_64BIT
314 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
316 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
318 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
319 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
320 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
321 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
322 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
323 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
324 CONFIG_SYS_BMAN_CENA_SIZE)
325 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
326 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
327 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
328 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
329 #ifdef CONFIG_PHYS_64BIT
330 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
332 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
334 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
335 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
336 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
337 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
338 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
339 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
340 CONFIG_SYS_QMAN_CENA_SIZE)
341 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
342 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
344 #define CONFIG_SYS_DPAA_FMAN
345 /* Default address of microcode for the Linux Fman driver */
347 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
348 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
349 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
351 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
352 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
354 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
355 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
357 #ifdef CONFIG_SYS_DPAA_FMAN
358 #define CONFIG_FMAN_ENET
362 #define CONFIG_PCI_INDIRECT_BRIDGE
364 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
365 #endif /* CONFIG_PCI */
368 #ifdef CONFIG_FSL_SATA_V2
369 #define CONFIG_SYS_SATA_MAX_DEVICE 2
371 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
372 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
374 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
375 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
380 #ifdef CONFIG_FMAN_ENET
381 #define CONFIG_SYS_TBIPA_VALUE 8
382 #define CONFIG_MII /* MII PHY management */
383 #define CONFIG_ETHPRIME "FM1@DTSEC4"
389 #define CONFIG_LOADS_ECHO /* echo on for serial download */
390 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
395 #define CONFIG_HAS_FSL_DR_USB
396 #define CONFIG_HAS_FSL_MPH_USB
398 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
399 #define CONFIG_USB_EHCI_FSL
400 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
401 #define CONFIG_EHCI_IS_TDI
402 /* _VIA_CONTROL_EP */
406 #define CONFIG_FSL_ESDHC
407 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
408 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
412 * Miscellaneous configurable options
414 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
417 * For booting Linux, the board info and command line data
418 * have to be in the first 64 MB of memory, since this is
419 * the maximum mapped by the Linux kernel during initialization.
421 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
422 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
424 #ifdef CONFIG_CMD_KGDB
425 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
429 * Environment Configuration
431 #define CONFIG_ROOTPATH "/opt/nfsroot"
432 #define CONFIG_BOOTFILE "uImage"
433 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
435 /* default location for tftp and bootm */
436 #define CONFIG_LOADADDR 1000000
438 #define __USB_PHY_TYPE utmi
440 #define CONFIG_EXTRA_ENV_SETTINGS \
441 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
442 "bank_intlv=cs0_cs1;" \
443 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
444 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
446 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
447 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
448 "consoledev=ttyS0\0" \
449 "ramdiskaddr=2000000\0" \
450 "fdtaddr=1e00000\0" \
453 #define CONFIG_HDBOOT \
454 "setenv bootargs root=/dev/$bdev rw " \
455 "console=$consoledev,$baudrate $othbootargs;" \
456 "tftp $loadaddr $bootfile;" \
457 "tftp $fdtaddr $fdtfile;" \
458 "bootm $loadaddr - $fdtaddr"
460 #define CONFIG_NFSBOOTCOMMAND \
461 "setenv bootargs root=/dev/nfs rw " \
462 "nfsroot=$serverip:$rootpath " \
463 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
464 "console=$consoledev,$baudrate $othbootargs;" \
465 "tftp $loadaddr $bootfile;" \
466 "tftp $fdtaddr $fdtfile;" \
467 "bootm $loadaddr - $fdtaddr"
469 #define CONFIG_RAMBOOTCOMMAND \
470 "setenv bootargs root=/dev/ram rw " \
471 "console=$consoledev,$baudrate $othbootargs;" \
472 "tftp $ramdiskaddr $ramdiskfile;" \
473 "tftp $loadaddr $bootfile;" \
474 "tftp $fdtaddr $fdtfile;" \
475 "bootm $loadaddr $ramdiskaddr $fdtaddr"
477 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
479 #include <asm/fsl_secure_boot.h>
481 #ifdef CONFIG_SECURE_BOOT
484 #endif /* __CONFIG_H */