2 * (C) Copyright 2000, 2001, 2002
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
5 * Configuration for the Cogent CSB226 board. For details see
6 * http://www.cogcomp.com/csb_csb226.htm
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * include/configs/csb226.h - configuration options, board specific
37 * If we are developing, we might want to start U-Boot from ram
38 * so we MUST NOT initialize critical regs like mem-timing ...
40 #define CONFIG_INIT_CRITICAL /* undef for developing */
43 * High Level Configuration Options
46 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
47 #define CONFIG_CSB226 1 /* on a CSB226 board */
49 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
50 /* for timer/console/ethernet */
56 * select serial console configuration
58 #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
60 /* allow to overwrite serial and ethaddr */
61 #define CONFIG_ENV_OVERWRITE
63 #define CONFIG_BAUDRATE 19200
64 #undef CONFIG_MISC_INIT_R /* not used yet */
66 #define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET)
68 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
69 #include <cmd_confdefs.h>
71 #define CONFIG_BOOTDELAY 3
72 #define CONFIG_BOOTARGS "console=ttyS0,19200 ip=dhcp root=/dev/nfs, ether=0,0x08000000,eth0"
73 #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
74 #define CONFIG_NETMASK 255.255.255.0
75 #define CONFIG_IPADDR 192.168.1.56
76 #define CONFIG_SERVERIP 192.168.1.2
77 #define CONFIG_BOOTCOMMAND "bootm 0x40000"
78 #define CONFIG_SHOW_BOOT_PROGRESS
80 #define CONFIG_CMDLINE_TAG 1
82 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
83 #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
84 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
88 * Miscellaneous configurable options
92 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
93 * used for the RAM copy of the uboot code
96 #define CFG_MALLOC_LEN (128*1024)
98 #define CFG_LONGHELP /* undef to save memory */
99 #define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
100 #define CFG_CBSIZE 128 /* Console I/O Buffer Size */
101 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
102 #define CFG_MAXARGS 16 /* max number of command args */
103 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
105 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
106 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
108 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
110 #define CFG_LOAD_ADDR 0xa3000000 /* default load address */
111 /* RS: where is this documented? */
112 /* RS: is this where U-Boot is */
113 /* RS: relocated to in RAM? */
115 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
116 /* RS: the oscillator is actually 3680130?? */
117 #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
119 /* ^^^^^ Memory Speed 99.53 MHz */
120 /* ^^ Run Mode Speed = 2x Mem Speed */
121 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
123 #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
125 /* valid baudrates */
126 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
131 * The stack sizes are set up in start.S using the settings below
133 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
134 #ifdef CONFIG_USE_IRQ
135 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
136 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
140 * Physical Memory Map
142 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
143 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
144 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
146 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
147 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
149 #define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
150 #define CFG_DRAM_SIZE 0x02000000
152 #define CFG_FLASH_BASE PHYS_FLASH_1
157 #define CFG_GPSR0_VAL 0xFFFFFFFF
158 #define CFG_GPSR1_VAL 0xFFFFFFFF
159 #define CFG_GPSR2_VAL 0xFFFFFFFF
160 #define CFG_GPCR0_VAL 0x08022080
161 #define CFG_GPCR1_VAL 0x00000000
162 #define CFG_GPCR2_VAL 0x00000000
163 #define CFG_GPDR0_VAL 0xCD82A878
164 #define CFG_GPDR1_VAL 0xFCFFAB80
165 #define CFG_GPDR2_VAL 0x0001FFFF
166 #define CFG_GAFR0_L_VAL 0x80000000
167 #define CFG_GAFR0_U_VAL 0xA5254010
168 #define CFG_GAFR1_L_VAL 0x599A9550
169 #define CFG_GAFR1_U_VAL 0xAAA5AAAA
170 #define CFG_GAFR2_L_VAL 0xAAAAAAAA
171 #define CFG_GAFR2_U_VAL 0x00000002
173 /* FIXME: set GPIO_RER/FER */
175 #define CFG_PSSR_VAL 0x20
180 #define CFG_MSC0_VAL 0x2EF025D0
181 #define CFG_MSC1_VAL 0x00003F64
182 #define CFG_MSC2_VAL 0x00000000
183 #define CFG_MDCNFG_VAL 0x09a909a9
184 #define CFG_MDREFR_VAL 0x03ca0030
185 #define CFG_MDMRS_VAL 0x00220022
188 * PCMCIA and CF Interfaces
190 #define CFG_MECR_VAL 0x00000000
191 #define CFG_MCMEM0_VAL 0x00000000
192 #define CFG_MCMEM1_VAL 0x00000000
193 #define CFG_MCATT0_VAL 0x00000000
194 #define CFG_MCATT1_VAL 0x00000000
195 #define CFG_MCIO0_VAL 0x00000000
196 #define CFG_MCIO1_VAL 0x00000000
198 #define CSB226_USER_LED0 0x00000008
199 #define CSB226_USER_LED1 0x00000010
200 #define CSB226_USER_LED2 0x00000020
204 * FLASH and environment organization
206 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
207 #define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
209 /* timeout values are in ticks */
210 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
211 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
213 #define CFG_ENV_IS_IN_FLASH 1
214 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
215 /* Addr of Environment Sector */
216 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
218 #endif /* __CONFIG_H */