3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * High Level Configuration Options
35 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
36 #define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */
38 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
40 /* we will never enable dcache, because we have to setup MMU first */
41 #define CONFIG_SYS_NO_DCACHE
44 * Size of malloc() pool
46 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
47 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
52 #define CONFIG_NET_MULTI
53 #define CONFIG_SMC91111
54 #define CONFIG_SMC91111_BASE 0x10000300
55 #define CONFIG_SMC91111_EXT_PHY
56 #define CONFIG_SMC_USE_32_BIT
59 * select serial console configuration
61 #define CONFIG_PXA_SERIAL
62 #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
64 /* allow to overwrite serial and ethaddr */
65 #define CONFIG_ENV_OVERWRITE
67 #define CONFIG_BAUDRATE 115200
73 #define CONFIG_BOOTP_BOOTFILESIZE
74 #define CONFIG_BOOTP_BOOTPATH
75 #define CONFIG_BOOTP_GATEWAY
76 #define CONFIG_BOOTP_HOSTNAME
80 * Command line configuration.
82 #include <config_cmd_default.h>
85 #define CONFIG_BOOTDELAY 3
86 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200"
87 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
88 #define CONFIG_NETMASK 255.255.0.0
89 #define CONFIG_IPADDR 192.168.0.21
90 #define CONFIG_SERVERIP 192.168.0.250
91 #define CONFIG_BOOTCOMMAND "bootm 40000"
92 #define CONFIG_CMDLINE_TAG
95 * Miscellaneous configurable options
97 #define CONFIG_SYS_LONGHELP /* undef to save memory */
98 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
99 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
100 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
101 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
102 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
104 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
105 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
107 #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
109 #define CONFIG_SYS_HZ 1000
110 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
112 /* valid baudrates */
113 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
118 * The stack sizes are set up in start.S using the settings below
120 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
121 #ifdef CONFIG_USE_IRQ
122 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
123 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
127 * Physical Memory Map
129 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
130 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
131 #define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
132 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
133 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
134 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
135 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
136 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
137 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
139 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
140 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
141 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
143 #define CONFIG_SYS_DRAM_BASE 0xa0000000
144 #define CONFIG_SYS_DRAM_SIZE 0x04000000
146 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
148 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
149 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
152 * FLASH and environment organization
154 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
155 #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
157 /* timeout values are in ticks */
158 #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
159 #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
161 #define CONFIG_ENV_IS_IN_FLASH 1
162 #define CONFIG_ENV_ADDR 0x00020000 /* absolute address for now */
163 #define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
165 /******************************************************************************
167 * CPU specific defines
169 ******************************************************************************/
174 * GPIO pin assignments
175 * GPIO Name Dir Out AF
198 * 22 PGMEN O 1 FIXME for debug only enable flash
218 * 42 RS232FOFF O 0 00
258 * NOTE: All NC's are defined to be outputs
261 /* Pin direction control */
262 /* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */
263 #define CONFIG_SYS_GPDR0_VAL 0xfff3bf02
264 #define CONFIG_SYS_GPDR1_VAL 0xfbffbf83
265 #define CONFIG_SYS_GPDR2_VAL 0x0001ffff
266 /* Set and Clear registers */
267 #define CONFIG_SYS_GPSR0_VAL 0x00400800
268 #define CONFIG_SYS_GPSR1_VAL 0x00000480
269 #define CONFIG_SYS_GPSR2_VAL 0x00014000
270 #define CONFIG_SYS_GPCR0_VAL 0x00000000
271 #define CONFIG_SYS_GPCR1_VAL 0x00000000
272 #define CONFIG_SYS_GPCR2_VAL 0x00000000
273 /* Edge detect registers (these are set by the kernel) */
274 #define CONFIG_SYS_GRER0_VAL 0x00000000
275 #define CONFIG_SYS_GRER1_VAL 0x00000000
276 #define CONFIG_SYS_GRER2_VAL 0x00000000
277 #define CONFIG_SYS_GFER0_VAL 0x00000000
278 #define CONFIG_SYS_GFER1_VAL 0x00000000
279 #define CONFIG_SYS_GFER2_VAL 0x00000000
280 /* Alternate function registers */
281 #define CONFIG_SYS_GAFR0_L_VAL 0x00000000
282 #define CONFIG_SYS_GAFR0_U_VAL 0x00000010
283 #define CONFIG_SYS_GAFR1_L_VAL 0x900a9550
284 #define CONFIG_SYS_GAFR1_U_VAL 0x00000008
285 #define CONFIG_SYS_GAFR2_L_VAL 0x20000000
286 #define CONFIG_SYS_GAFR2_U_VAL 0x00000002
289 * Clocks, power control and interrupts
291 #define CONFIG_SYS_PSSR_VAL 0x00000020
292 #define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
293 #define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
294 #define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
306 * FIXME Can ethernet be burst read and/or write?? This is set for lubbock
307 * Verify timings on all
309 #define CONFIG_SYS_MSC0_VAL 0x000023FA /* flash bank (cs0) */
310 /*#define CONFIG_SYS_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */
311 #define CONFIG_SYS_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */
312 #define CONFIG_SYS_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */
314 #define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
315 #define CONFIG_SYS_MDMRS_VAL 0x00000000
316 #define CONFIG_SYS_MDREFR_VAL 0x00018018
318 #define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */
319 #define CONFIG_SYS_MDMRS_VAL 0x00000000
320 #define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
324 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
326 #define CONFIG_SYS_MECR_VAL 0x00000000
327 #define CONFIG_SYS_MCMEM0_VAL 0x00010504
328 #define CONFIG_SYS_MCMEM1_VAL 0x00010504
329 #define CONFIG_SYS_MCATT0_VAL 0x00010504
330 #define CONFIG_SYS_MCATT1_VAL 0x00010504
331 #define CONFIG_SYS_MCIO0_VAL 0x00004715
332 #define CONFIG_SYS_MCIO1_VAL 0x00004715
334 /* Board specific defines */
346 /* SuperIO defines */
347 #define CRADLE_SIO_INDEX 0x2e
348 #define CRADLE_SIO_DATA 0x2f
351 #define CRADLE_CPLD_PHYS 0x08000000
352 #define CRADLE_SIO1_PHYS 0x08100000
353 #define CRADLE_SIO2_PHYS 0x08200000
354 #define CRADLE_SIO3_PHYS 0x08300000
355 #define CRADLE_ETH_PHYS 0x10000000
359 /* global prototypes */
360 void led_code(int code, int color);
364 #endif /* __CONFIG_H */