NAND: remove NAND_MAX_CHIPS definitions
[platform/kernel/u-boot.git] / include / configs / cpu9260.h
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Ilko Iliev <www.ronetix.at>
6  *
7  * (C) Copyright 2009
8  * Eric Benard <eric@eukrea.com>
9  *
10  * Configuration settings for the Eukrea CPU9260 board.
11  *
12  * See file CREDITS for list of people who contributed to this
13  * project.
14  *
15  * This program is free software; you can redistribute it and/or
16  * modify it under the terms of the GNU General Public License as
17  * published by the Free Software Foundation; either version 2 of
18  * the License, or (at your option) any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; if not, write to the Free Software
27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28  * MA 02111-1307 USA
29  */
30
31 #ifndef __CONFIG_H
32 #define __CONFIG_H
33
34 /* to be removed once maemory-map.h is fixed */
35 #define AT91_BASE_SYS   0xffffe800
36 #define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
37
38 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
39 #define CONFIG_SYS_HZ           1000
40 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
41
42 #if defined(CONFIG_CPU9G20)
43 #define CONFIG_AT91SAM9G20
44 #elif defined(CONFIG_CPU9260)
45 #define CONFIG_AT91SAM9260
46 #else
47 #error "Unknown board"
48 #endif
49
50 #include <asm/arch/hardware.h>
51
52 #define CONFIG_AT91FAMILY
53 #define CONFIG_ARCH_CPU_INIT
54 #undef CONFIG_USE_IRQ
55 #define CONFIG_DISPLAY_CPUINFO
56 #define CONFIG_BOARD_EARLY_INIT_F
57
58 #define CONFIG_CMDLINE_TAG
59 #define CONFIG_SETUP_MEMORY_TAGS
60 #define CONFIG_INITRD_TAG
61
62 #if defined(CONFIG_NANDBOOT)
63 #define CONFIG_SKIP_LOWLEVEL_INIT
64 #define CONFIG_SYS_TEXT_BASE           0x23f00000
65 #else
66 #define CONFIG_SYS_TEXT_BASE           0x00000000
67 #endif
68
69 /* clocks */
70 #if defined(CONFIG_CPU9G20)
71 #define MASTER_PLL_DIV          0x01
72 #define MASTER_PLL_MUL          0x2B
73 #elif defined(CONFIG_CPU9260)
74 #define MASTER_PLL_DIV          0x09
75 #define MASTER_PLL_MUL          0x61
76 #endif
77
78 /* CKGR_MOR - enable main osc. */
79 #define CONFIG_SYS_MOR_VAL                                              \
80                 (AT91_PMC_MOSCEN |                                      \
81                  (255 << 8))            /* Main Oscillator Start-up Time */
82 #if defined(CONFIG_CPU9G20)
83 #define CONFIG_SYS_PLLAR_VAL                                            \
84                 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
85                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
86 #elif defined(CONFIG_CPU9260)
87 #define CONFIG_SYS_PLLAR_VAL                                            \
88                 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
89                  AT91_PMC_OUT |                                         \
90                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
91 #endif
92
93 #if defined(CONFIG_CPU9G20)
94 #define CONFIG_SYS_MCKR1_VAL            \
95                 (AT91_PMC_CSS_PLLA |    \
96                  AT91_PMC_PRES_1 |      \
97                  AT91SAM9_PMC_MDIV_6 |  \
98                  AT91_PMC_PDIV_2)
99 #define CONFIG_SYS_MCKR2_VAL            \
100                 CONFIG_SYS_MCKR1_VAL
101 #elif defined(CONFIG_CPU9260)
102 #define CONFIG_SYS_MCKR1_VAL            \
103                 (AT91_PMC_CSS_SLOW |    \
104                  AT91_PMC_PRES_1 |      \
105                  AT91SAM9_PMC_MDIV_2 |  \
106                  AT91_PMC_PDIV_1)
107 #define CONFIG_SYS_MCKR2_VAL            \
108                 (AT91_PMC_CSS_PLLA |    \
109                  AT91_PMC_PRES_1 |      \
110                  AT91SAM9_PMC_MDIV_2 |  \
111                  AT91_PMC_PDIV_1)
112 #endif
113
114 /* define PDC[31:16] as DATA[31:16] */
115 #define CONFIG_SYS_PIOC_PDR_VAL1        0xFFFF0000
116 /* no pull-up for D[31:16] */
117 #define CONFIG_SYS_PIOC_PPUDR_VAL       0xFFFF0000
118
119 /* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
120 #define CONFIG_SYS_MATRIX_EBICSA_VAL            \
121                 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
122                 AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
123
124 /* SDRAM */
125 /* SDRAMC_MR Mode register */
126 #define CONFIG_SYS_SDRC_MR_VAL1         AT91_SDRAMC_MODE_NORMAL
127 /* SDRAMC_TR - Refresh Timer register */
128 #define CONFIG_SYS_SDRC_TR_VAL1         0x287
129 /* SDRAMC_CR - Configuration register*/
130 #if defined(CONFIG_CPU9G20)
131 #define CONFIG_SYS_SDRC_CR_VAL_64MB                                     \
132                 (AT91_SDRAMC_NC_9 |                                     \
133                  AT91_SDRAMC_NR_13 |                                    \
134                  AT91_SDRAMC_NB_4 |                                     \
135                  AT91_SDRAMC_CAS_2 |                                    \
136                  AT91_SDRAMC_DBW_32 |                                   \
137                  (2 <<  8) |    /* Write Recovery Delay */              \
138                  (9 << 12) |    /* Row Cycle Delay */                   \
139                  (3 << 16) |    /* Row Precharge Delay */               \
140                  (3 << 20) |    /* Row to Column Delay */               \
141                  (6 << 24) |    /* Active to Precharge Delay */         \
142                  (10 << 28))    /* Exit Self Refresh to Active Delay */
143
144 #define CONFIG_SYS_SDRC_CR_VAL_128MB                                    \
145                 (AT91_SDRAMC_NC_10 |                                    \
146                  AT91_SDRAMC_NR_13 |                                    \
147                  AT91_SDRAMC_NB_4 |                                     \
148                  AT91_SDRAMC_CAS_2 |                                    \
149                  AT91_SDRAMC_DBW_32 |                                   \
150                  (2 <<  8) |    /* Write Recovery Delay */              \
151                  (9 << 12) |    /* Row Cycle Delay */                   \
152                  (3 << 16) |    /* Row Precharge Delay */               \
153                  (3 << 20) |    /* Row to Column Delay */               \
154                  (6 << 24) |    /* Active to Precharge Delay */         \
155                  (10 << 28))    /* Exit Self Refresh to Active Delay */
156 #elif defined(CONFIG_CPU9260)
157 #define CONFIG_SYS_SDRC_CR_VAL_64MB                                     \
158                 (AT91_SDRAMC_NC_9 |                                     \
159                  AT91_SDRAMC_NR_13 |                                    \
160                  AT91_SDRAMC_NB_4 |                                     \
161                  AT91_SDRAMC_CAS_2 |                                    \
162                  AT91_SDRAMC_DBW_32 |                                   \
163                  (2 <<  8) |    /* Write Recovery Delay */              \
164                  (7 << 12) |    /* Row Cycle Delay */                   \
165                  (2 << 16) |    /* Row Precharge Delay */               \
166                  (2 << 20) |    /* Row to Column Delay */               \
167                  (5 << 24) |    /* Active to Precharge Delay */         \
168                  (8 << 28))     /* Exit Self Refresh to Active Delay */
169
170 #define CONFIG_SYS_SDRC_CR_VAL_128MB                                    \
171                 (AT91_SDRAMC_NC_10 |                                    \
172                  AT91_SDRAMC_NR_13 |                                    \
173                  AT91_SDRAMC_NB_4 |                                     \
174                  AT91_SDRAMC_CAS_2 |                                    \
175                  AT91_SDRAMC_DBW_32 |                                   \
176                  (2 <<  8) |    /* Write Recovery Delay */              \
177                  (7 << 12) |    /* Row Cycle Delay */                   \
178                  (2 << 16) |    /* Row Precharge Delay */               \
179                  (2 << 20) |    /* Row to Column Delay */               \
180                  (5 << 24) |    /* Active to Precharge Delay */         \
181                  (8 << 28))     /* Exit Self Refresh to Active Delay */
182 #endif
183
184 /* Memory Device Register -> SDRAM */
185 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
186 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
187 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
188 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
189 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
190 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
191 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
192 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
193 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
194 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
195 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
196 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
197 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
198 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
199 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
200 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
201 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
202 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
203
204 /* setup SMC0, CS0 (NOR Flash) - 16-bit */
205 #if defined(CONFIG_CPU9G20)
206 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
207                 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |     \
208                  AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
209 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
210                 (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) |     \
211                  AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
212 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
213                 (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
214 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
215                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
216                  AT91_SMC_MODE_DBW_16 |                         \
217                  AT91_SMC_MODE_TDF |                            \
218                  AT91_SMC_MODE_TDF_CYCLE(3))
219 #elif defined(CONFIG_CPU9260)
220 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
221                 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |     \
222                  AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
223 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
224                 (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) |     \
225                  AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
226 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
227                 (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
228 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
229                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
230                  AT91_SMC_MODE_DBW_16 |                         \
231                  AT91_SMC_MODE_TDF |                            \
232                  AT91_SMC_MODE_TDF_CYCLE(2))
233 #endif
234
235 /* user reset enable */
236 #define CONFIG_SYS_RSTC_RMR_VAL                 \
237                 (AT91_RSTC_KEY |                \
238                 AT91_RSTC_CR_PROCRST |          \
239                 AT91_RSTC_MR_ERSTL(1) | \
240                 AT91_RSTC_MR_ERSTL(2))
241
242 /* Disable Watchdog */
243 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
244                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
245                  AT91_WDT_MR_WDV(0xfff) |                       \
246                  AT91_WDT_MR_WDDIS |                            \
247                  AT91_WDT_MR_WDD(0xfff))
248
249 /*
250  * Hardware drivers
251  */
252 #define CONFIG_AT91SAM9_WATCHDOG
253 #define CONFIG_AT91_GPIO
254 #define CONFIG_ATMEL_USART
255 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
256 #define CONFIG_USART_ID         ATMEL_ID_SYS
257
258 #define CONFIG_BOOTDELAY        3
259
260 /*
261  * BOOTP options
262  */
263 #define CONFIG_BOOTP_BOOTFILESIZE
264 #define CONFIG_BOOTP_BOOTPATH
265 #define CONFIG_BOOTP_GATEWAY
266 #define CONFIG_BOOTP_HOSTNAME
267
268 /*
269  * Command line configuration.
270  */
271 #include <config_cmd_default.h>
272 #undef CONFIG_CMD_BDI
273 #undef CONFIG_CMD_IMI
274 #undef CONFIG_CMD_FPGA
275 #undef CONFIG_CMD_LOADS
276 #undef CONFIG_CMD_IMLS
277
278 #define CONFIG_CMD_PING
279 #define CONFIG_CMD_DHCP
280 #define CONFIG_CMD_NAND
281 #define CONFIG_CMD_USB
282 #define CONFIG_CMD_FAT
283 #define CONFIG_CMD_MII
284
285 /* SDRAM */
286 #define CONFIG_NR_DRAM_BANKS    1
287 #define CONFIG_SYS_SDRAM_BASE           0x20000000
288 #if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
289 #define CONFIG_SYS_SDRAM_SIZE           (128 * 1024 * 1024)
290 #define CONFIG_SYS_SDRC_CR_VAL  CONFIG_SYS_SDRC_CR_VAL_128MB
291 #else
292 #define CONFIG_SYS_SDRAM_SIZE           (64 * 1024 * 1024)
293 #define CONFIG_SYS_SDRC_CR_VAL  CONFIG_SYS_SDRC_CR_VAL_64MB
294 #endif
295
296 /* NAND flash */
297 #define CONFIG_NAND_ATMEL
298 #define CONFIG_SYS_MAX_NAND_DEVICE              1
299 #define CONFIG_SYS_NAND_BASE                    0x40000000
300 #define CONFIG_SYS_NAND_DBW_8                   1
301 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIO_PORTC, 13
302 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIO_PORTC, 14
303 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
304 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
305
306 /* NOR flash */
307 #if defined(CONFIG_NANDBOOT)
308 #define CONFIG_SYS_NO_FLASH
309 #else
310 #define CONFIG_SYS_FLASH_CFI
311 #define CONFIG_FLASH_CFI_DRIVER
312 #define PHYS_FLASH_1                            0x10000000
313 #define PHYS_FLASH_2                            0x12000000
314 #define CONFIG_SYS_FLASH_BANKS_LIST             \
315                 { PHYS_FLASH_1, PHYS_FLASH_2 }
316 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
317 #define CONFIG_SYS_MAX_FLASH_SECT               (255+4)
318 #define CONFIG_SYS_MAX_FLASH_BANKS              2
319 #define CONFIG_SYS_FLASH_CFI_WIDTH              FLASH_CFI_16BIT
320 #define CONFIG_SYS_FLASH_EMPTY_INFO
321 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
322 #define CONFIG_SYS_FLASH_PROTECTION
323 #define CONFIG_SYS_MONITOR_BASE                 PHYS_FLASH_1
324 #endif
325
326 /* Ethernet */
327 #define CONFIG_MACB
328 #define CONFIG_RMII
329 #define CONFIG_NET_RETRY_COUNT                  20
330 #define CONFIG_MACB_SEARCH_PHY
331
332 /* LEDS */
333 /* Status LED */
334 #define CONFIG_STATUS_LED
335 #define CONFIG_BOARD_SPECIFIC_LED
336 #define STATUS_LED_RED                          0
337 #define STATUS_LED_GREEN                        1
338 #define STATUS_LED_YELLOW                       2
339 #define STATUS_LED_BLUE                         3
340 /* Red */
341 #define STATUS_LED_BIT                          STATUS_LED_RED
342 #define STATUS_LED_STATE                        STATUS_LED_OFF
343 #define STATUS_LED_PERIOD                       (CONFIG_SYS_HZ / 2)
344 /* Green */
345 #define STATUS_LED_BIT1                         STATUS_LED_GREEN
346 #define STATUS_LED_STATE1                       STATUS_LED_OFF
347 #define STATUS_LED_PERIOD1                      (CONFIG_SYS_HZ / 2)
348 /* Yellow */
349 #define STATUS_LED_BIT2                         STATUS_LED_YELLOW
350 #define STATUS_LED_STATE2                       STATUS_LED_OFF
351 #define STATUS_LED_PERIOD2                      (CONFIG_SYS_HZ / 2)
352 /* Blue */
353 #define STATUS_LED_BIT3                         STATUS_LED_BLUE
354 #define STATUS_LED_STATE3                       STATUS_LED_ON
355 #define STATUS_LED_PERIOD3                      (CONFIG_SYS_HZ / 2)
356 /* Optional value */
357 #define STATUS_LED_BOOT                         STATUS_LED_BIT
358
359 #define CONFIG_RED_LED                          AT91_PIO_PORTC, 11
360 #define CONFIG_GREEN_LED                        AT91_PIO_PORTC, 12
361 #define CONFIG_YELLOW_LED                       AT91_PIO_PORTC, 7
362 #define CONFIG_BLUE_LED                         AT91_PIO_PORTC, 9
363
364 /* USB */
365 #define CONFIG_USB_ATMEL
366 #define CONFIG_USB_OHCI_NEW
367 #define CONFIG_DOS_PARTITION
368 #define CONFIG_SYS_USB_OHCI_CPU_INIT
369 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
370 #if defined(CONFIG_CPU9G20)
371 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9g20"
372 #elif defined(CONFIG_CPU9260)
373 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9260"
374 #endif
375 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
376 #define CONFIG_USB_STORAGE
377
378 #define CONFIG_SYS_LOAD_ADDR                    0x21000000
379 #define CONFIG_LOADADDR                         CONFIG_SYS_LOAD_ADDR
380
381 #define CONFIG_SYS_MEMTEST_START                CONFIG_SYS_SDRAM_BASE
382 #define CONFIG_SYS_MEMTEST_END                  \
383         (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
384
385 #if defined(CONFIG_NANDBOOT)
386 #define CONFIG_SYS_USE_NANDFLASH
387 #undef CONFIG_SYS_USE_FLASH
388 #else
389 #define CONFIG_SYS_USE_FLASH
390 #undef CONFIG_SYS_USE_NANDFLASH
391 #endif
392
393 #if defined(CONFIG_CPU9G20)
394 #define CONFIG_SYS_BASEDIR      "cpu9G20"
395 #elif defined(CONFIG_CPU9260)
396 #define CONFIG_SYS_BASEDIR      "cpu9260"
397 #endif
398
399 #if defined(CONFIG_SYS_USE_FLASH)
400 #define CONFIG_ENV_IS_IN_FLASH
401 #define CONFIG_ENV_OFFSET               0x40000
402 #define CONFIG_ENV_SECT_SIZE            0x20000
403 #define CONFIG_ENV_SIZE                 0x20000
404 #define CONFIG_ENV_OVERWRITE
405
406 #define CONFIG_BOOTCOMMAND              "run flashboot"
407
408 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=atmel_nand"
409 #define MTDPARTS_DEFAULT                \
410         "mtdparts=physmap-flash.0:"     \
411                 "256k(u-boot)ro,"       \
412                 "128k(u-boot-env)ro,"   \
413                 "1792k(kernel),"        \
414                 "-(rootfs);"            \
415         "atmel_nand:-(nand)"
416
417 #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
418
419 #define CONFIG_EXTRA_ENV_SETTINGS                               \
420         "mtdids=" MTDIDS_DEFAULT "\0"                           \
421         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
422         "partition=nand0,0\0"                                   \
423         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
424         "ramboot=tftpboot 0x22000000 $(basedir)/uImage;"        \
425                 "run ramargs;bootm 22000000\0"                  \
426         "flashboot=run ramargs;bootm 0x10060000\0"              \
427         "basedir=" CONFIG_SYS_BASEDIR "\0"                      \
428         "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
429                 "off 0x10000000 0x1003ffff;erase 0x10000000 "   \
430                 "0x1003ffff;cp.b 0x24000000 0x10000000 "        \
431                 "$(filesize)\0" \
432         "updtui=tftp 0x24000000 $(basedir)/uImage;protect off"  \
433                 " 0x10060000 0x1021ffff;erase 0x10060000 "      \
434                 "0x1021ffff;cp.b 0x24000000 0x10060000 "        \
435                 "$(filesize)\0" \
436         "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; "     \
437                 "protect off 0x10220000 0x13ffffff;erase "      \
438                 "0x10220000 0x13ffffff;cp.b 0x24000000 "        \
439                 "0x10220000 $(filesize)\0" \
440         ""
441 #elif defined(CONFIG_NANDBOOT)
442 #define CONFIG_ENV_IS_IN_NAND
443 #define CONFIG_ENV_OFFSET               0x60000
444 #define CONFIG_ENV_OFFSET_REDUND        0x80000
445 #define CONFIG_ENV_SECT_SIZE            0x20000
446 #define CONFIG_ENV_SIZE                 0x20000
447 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
448 #define CONFIG_ENV_OVERWRITE
449
450 #define CONFIG_BOOTCOMMAND              "run flashboot"
451
452 #define MTDIDS_DEFAULT          "nand0=atmel_nand"
453 #define MTDPARTS_DEFAULT                \
454         "mtdparts=atmel_nand:"          \
455                 "128k(bootstrap)ro,"    \
456                 "256k(u-boot)ro,"       \
457                 "128k(u-boot-env)ro,"   \
458                 "128k(u-boot-env2)ro,"  \
459                 "2M(kernel),"   \
460                 "-(rootfs)"
461
462 #define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs "      \
463         "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
464
465 #define CONFIG_EXTRA_ENV_SETTINGS                               \
466         "mtdids=" MTDIDS_DEFAULT "\0"                           \
467         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
468         "partition=nand0,5\0"                                   \
469         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
470         "ramboot=tftpboot 0x22000000 $(basedir)/uImage;"        \
471                 "run ramargs;bootm 22000000\0"                  \
472         "flashboot=run ramargs; nand read 0x22000000 0xA0000 "  \
473                 "0x200000; bootm 0x22000000\0"                  \
474         "basedir=" CONFIG_SYS_BASEDIR "\0"                      \
475         "u-boot=u-boot-eukrea-cpu9260.bin\0"                    \
476         "kernel=uImage-eukrea-cpu9260.bin\0"                    \
477         "rootfs=image-eukrea-cpu9260.ubi\0"                     \
478         "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; "        \
479                 "nand erase 20000 40000; "                      \
480                 "nand write ${loadaddr} 20000 40000\0"          \
481         "updtui=tftp ${loadaddr} $(basedir)/${kernel}; "        \
482                 "nand erase a0000 200000; "                     \
483                 "nand write ${loadaddr} a0000 200000\0"         \
484         "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; "       \
485                 "nand erase  2a0000 fd60000; "                  \
486                 "nand write ${loadaddr} 2a0000 ${filesize}\0"
487 #endif
488
489 #define CONFIG_BAUDRATE                 115200
490 #define CONFIG_SYS_BAUDRATE_TABLE       {115200 , 19200, 38400, 57600, 9600 }
491
492 #if defined(CONFIG_CPU9G20)
493 #define CONFIG_SYS_PROMPT               "CPU9G20=> "
494 #elif defined(CONFIG_CPU9260)
495 #define CONFIG_SYS_PROMPT               "CPU9260=> "
496 #endif
497 #define CONFIG_SYS_CBSIZE               256
498 #define CONFIG_SYS_MAXARGS              16
499 #define CONFIG_SYS_PBSIZE               \
500                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
501 #define CONFIG_SYS_LONGHELP
502 #define CONFIG_CMDLINE_EDITING
503 #define CONFIG_SILENT_CONSOLE
504 #define CONFIG_NETCONSOLE
505
506 /*
507  * Size of malloc() pool
508  */
509 #define CONFIG_SYS_MALLOC_LEN           \
510                 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
511
512 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
513                                 GENERATED_GBL_DATA_SIZE)
514
515 #define CONFIG_STACKSIZE                (32 * 1024)
516
517 #if defined(CONFIG_USE_IRQ)
518 #error CONFIG_USE_IRQ not supported
519 #endif
520
521 #endif