1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Common board functions for siemens AT91SAM9G45 based boards
4 * (C) Copyright 2013 Siemens AG
7 * U-Boot file: include/configs/at91sam9m10g45ek.h
8 * (C) Copyright 2007-2008
9 * Stelian Pop <stelian@popies.net>
10 * Lead Tech Design <www.leadtechdesign.com>
16 #include <asm/hardware.h>
17 #include <linux/sizes.h>
20 * Warning: changing CONFIG_SYS_TEXT_BASE requires
21 * adapting the initial boot program.
22 * Since the linker has to swallow that define, we must use a pure
26 /* ARM asynchronous clock */
27 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
28 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
31 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
32 #define CONFIG_USART_ID ATMEL_ID_SYS
35 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
36 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
38 #define CONFIG_SYS_INIT_SP_ADDR \
39 (CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE)
42 #ifdef CONFIG_CMD_NAND
43 #define CONFIG_SYS_MAX_NAND_DEVICE 1
44 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
45 #define CONFIG_SYS_NAND_DBW_8
47 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
49 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
50 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
51 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
54 /* DFU class support */
55 #define DFU_MANIFEST_POLL_TIMEOUT 25000
57 /* bootstrap + u-boot + env in nandflash */
60 #define CONFIG_SPL_MAX_SIZE (12 * SZ_1K)
61 #define CONFIG_SPL_STACK (SZ_16K)
63 #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
64 #define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K)
66 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
67 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
68 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
70 #define CONFIG_SYS_NAND_ECCSIZE 256
71 #define CONFIG_SYS_NAND_ECCBYTES 3
72 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
73 48, 49, 50, 51, 52, 53, 54, 55, \
74 56, 57, 58, 59, 60, 61, 62, 63, }
76 #define CONFIG_SYS_MASTER_CLOCK 132096000
77 #define AT91_PLL_LOCK_TIMEOUT 1000000
78 #define CONFIG_SYS_AT91_PLLA 0x20c73f03
79 #define CONFIG_SYS_MCKR 0x1301
80 #define CONFIG_SYS_MCKR_CSS 0x1302
82 #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
83 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO