1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Common board functions for siemens AT91SAM9G45 based boards
4 * (C) Copyright 2013 Siemens AG
7 * U-Boot file: include/configs/at91sam9m10g45ek.h
8 * (C) Copyright 2007-2008
9 * Stelian Pop <stelian@popies.net>
10 * Lead Tech Design <www.leadtechdesign.com>
16 #include <asm/hardware.h>
17 #include <linux/sizes.h>
20 * Warning: changing CONFIG_SYS_TEXT_BASE requires
21 * adapting the initial boot program.
22 * Since the linker has to swallow that define, we must use a pure
26 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
28 /* ARM asynchronous clock */
29 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
30 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
32 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
33 #define CONFIG_SETUP_MEMORY_TAGS
34 #define CONFIG_INITRD_TAG
35 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
37 /* general purpose I/O */
38 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
39 #define CONFIG_AT91_GPIO
40 #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
43 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
44 #define CONFIG_USART_ID ATMEL_ID_SYS
47 #define CONFIG_AT91_LED
48 #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */
49 #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
55 #define CONFIG_BOOTP_BOOTFILESIZE
58 #define CONFIG_NR_DRAM_BANKS 1
59 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
60 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
62 #define CONFIG_SYS_INIT_SP_ADDR \
63 (CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE)
66 #ifdef CONFIG_CMD_NAND
67 #define CONFIG_NAND_ATMEL
68 #define CONFIG_SYS_MAX_NAND_DEVICE 1
69 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
70 #define CONFIG_SYS_NAND_DBW_8
72 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
74 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
75 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
76 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
82 #define CONFIG_NET_RETRY_COUNT 20
83 #define CONFIG_AT91_WANTS_COMMON_PHY
85 #define CONFIG_MTD_DEVICE
86 #define CONFIG_MTD_PARTITIONS
88 /* DFU class support */
89 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
90 #define DFU_MANIFEST_POLL_TIMEOUT 25000
92 #define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
94 /* bootstrap + u-boot + env in nandflash */
95 #define CONFIG_ENV_OFFSET 0x100000
96 #define CONFIG_ENV_OFFSET_REDUND 0x180000
97 #define CONFIG_ENV_SIZE SZ_128K
99 #define CONFIG_BOOTCOMMAND \
100 "nand read 0x70000000 0x200000 0x300000;" \
104 * Size of malloc() pool
106 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
109 /* Defines for SPL */
110 #define CONFIG_SPL_TEXT_BASE 0x300000
111 #define CONFIG_SPL_MAX_SIZE (12 * SZ_1K)
112 #define CONFIG_SPL_STACK (SZ_16K)
114 #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
115 #define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K)
117 #define CONFIG_SPL_NAND_DRIVERS
118 #define CONFIG_SPL_NAND_BASE
119 #define CONFIG_SPL_NAND_ECC
120 #define CONFIG_SPL_NAND_RAW_ONLY
121 #define CONFIG_SPL_NAND_SOFTECC
122 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
123 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
124 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
125 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
126 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
128 #define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
129 #define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
130 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
131 CONFIG_SYS_NAND_PAGE_SIZE)
132 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
133 #define CONFIG_SYS_NAND_ECCSIZE 256
134 #define CONFIG_SYS_NAND_ECCBYTES 3
135 #define CONFIG_SYS_NAND_OOBSIZE 64
136 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
137 48, 49, 50, 51, 52, 53, 54, 55, \
138 56, 57, 58, 59, 60, 61, 62, 63, }
140 #define CONFIG_SPL_ATMEL_SIZE
141 #define CONFIG_SYS_MASTER_CLOCK 132096000
142 #define AT91_PLL_LOCK_TIMEOUT 1000000
143 #define CONFIG_SYS_AT91_PLLA 0x20c73f03
144 #define CONFIG_SYS_MCKR 0x1301
145 #define CONFIG_SYS_MCKR_CSS 0x1302