include/configs/corenet_ds.h

   1 /*
   2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include "../board/freescale/common/ics307_clk.h"
  14
  15 #ifdef CONFIG_RAMBOOT_PBL
  16 #ifdef CONFIG_SECURE_BOOT
  17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  19 #ifdef CONFIG_NAND
  20 #define CONFIG_RAMBOOT_NAND
  21 #endif
  22 #define CONFIG_BOOTSCRIPT_COPY_RAM
  23 #else
  24 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  25 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  27 #if defined(CONFIG_TARGET_P3041DS)
  28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  29 #elif defined(CONFIG_TARGET_P4080DS)
  30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  31 #elif defined(CONFIG_TARGET_P5020DS)
  32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  33 #elif defined(CONFIG_TARGET_P5040DS)
  34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  35 #endif
  36 #endif
  37 #endif
  38
  39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  40 /* Set 1M boot space */
  41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  43                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  45 #endif
  46
  47 /* High Level Configuration Options */
  48 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  49 #define CONFIG_MP                       /* support multiple processors */
  50
  51 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  52 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  53 #endif
  54
  55 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  56 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  57 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  58 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  59 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  60 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  61
  62 #define CONFIG_ENV_OVERWRITE
  63
  64 #ifndef CONFIG_MTD_NOR_FLASH
  65 #else
  66 #define CONFIG_FLASH_CFI_DRIVER
  67 #define CONFIG_SYS_FLASH_CFI
  68 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  69 #endif
  70
  71 #if defined(CONFIG_SPIFLASH)
  72 #define CONFIG_SYS_EXTRA_ENV_RELOC
  73 #define CONFIG_ENV_SPI_BUS              0
  74 #define CONFIG_ENV_SPI_CS               0
  75 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  76 #define CONFIG_ENV_SPI_MODE             0
  77 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  78 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  79 #define CONFIG_ENV_SECT_SIZE            0x10000
  80 #elif defined(CONFIG_SDCARD)
  81 #define CONFIG_SYS_EXTRA_ENV_RELOC
  82 #define CONFIG_FSL_FIXED_MMC_LOCATION
  83 #define CONFIG_SYS_MMC_ENV_DEV          0
  84 #define CONFIG_ENV_SIZE                 0x2000
  85 #define CONFIG_ENV_OFFSET               (512 * 1658)
  86 #elif defined(CONFIG_NAND)
  87 #define CONFIG_SYS_EXTRA_ENV_RELOC
  88 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
  89 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  90 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  91 #define CONFIG_ENV_ADDR         0xffe20000
  92 #define CONFIG_ENV_SIZE         0x2000
  93 #elif defined(CONFIG_ENV_IS_NOWHERE)
  94 #define CONFIG_ENV_SIZE         0x2000
  95 #else
  96 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  97 #define CONFIG_ENV_SIZE         0x2000
  98 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  99 #endif
 100
 101 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 102
 103 /*
 104  * These can be toggled for performance analysis, otherwise use default.
 105  */
 106 #define CONFIG_SYS_CACHE_STASHING
 107 #define CONFIG_BACKSIDE_L2_CACHE
 108 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 109 #define CONFIG_BTB                      /* toggle branch predition */
 110 #define CONFIG_DDR_ECC
 111 #ifdef CONFIG_DDR_ECC
 112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 113 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 114 #endif
 115
 116 #define CONFIG_ENABLE_36BIT_PHYS
 117
 118 #ifdef CONFIG_PHYS_64BIT
 119 #define CONFIG_ADDR_MAP
 120 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 121 #endif
 122
 123 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 124 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 125 #define CONFIG_SYS_MEMTEST_END          0x00400000
 126
 127 /*
 128  *  Config the L3 Cache as L3 SRAM
 129  */
 130 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 131 #ifdef CONFIG_PHYS_64BIT
 132 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 133 #else
 134 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 135 #endif
 136 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 137 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 138
 139 #ifdef CONFIG_PHYS_64BIT
 140 #define CONFIG_SYS_DCSRBAR              0xf0000000
 141 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 142 #endif
 143
 144 /* EEPROM */
 145 #define CONFIG_ID_EEPROM
 146 #define CONFIG_SYS_I2C_EEPROM_NXID
 147 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 148 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 150
 151 /*
 152  * DDR Setup
 153  */
 154 #define CONFIG_VERY_BIG_RAM
 155 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 156 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 157
 158 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 159 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 160
 161 #define CONFIG_DDR_SPD
 162
 163 #define CONFIG_SYS_SPD_BUS_NUM  1
 164 #define SPD_EEPROM_ADDRESS1     0x51
 165 #define SPD_EEPROM_ADDRESS2     0x52
 166 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 167 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 168
 169 /*
 170  * Local Bus Definitions
 171  */
 172
 173 /* Set the local bus clock 1/8 of platform clock */
 174 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 175
 176 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 177 #ifdef CONFIG_PHYS_64BIT
 178 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 179 #else
 180 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 181 #endif
 182
 183 #define CONFIG_SYS_FLASH_BR_PRELIM \
 184                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 185                  | BR_PS_16 | BR_V)
 186 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 187                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 188
 189 #define CONFIG_SYS_BR1_PRELIM \
 190         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 191 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 192
 193 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 194 #ifdef CONFIG_PHYS_64BIT
 195 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 196 #else
 197 #define PIXIS_BASE_PHYS         PIXIS_BASE
 198 #endif
 199
 200 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 201 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 202
 203 #define PIXIS_LBMAP_SWITCH      7
 204 #define PIXIS_LBMAP_MASK        0xf0
 205 #define PIXIS_LBMAP_SHIFT       4
 206 #define PIXIS_LBMAP_ALTBANK     0x40
 207
 208 #define CONFIG_SYS_FLASH_QUIET_TEST
 209 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 210
 211 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 212 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 213 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 214 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 215
 216 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 217
 218 #if defined(CONFIG_RAMBOOT_PBL)
 219 #define CONFIG_SYS_RAMBOOT
 220 #endif
 221
 222 /* Nand Flash */
 223 #ifdef CONFIG_NAND_FSL_ELBC
 224 #define CONFIG_SYS_NAND_BASE            0xffa00000
 225 #ifdef CONFIG_PHYS_64BIT
 226 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 227 #else
 228 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 229 #endif
 230
 231 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 232 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 233 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 234
 235 /* NAND flash config */
 236 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 237                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 238                                | BR_PS_8               /* Port Size = 8 bit */ \
 239                                | BR_MS_FCM             /* MSEL = FCM */ \
 240                                | BR_V)                 /* valid */
 241 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 242                                | OR_FCM_PGS            /* Large Page*/ \
 243                                | OR_FCM_CSCT \
 244                                | OR_FCM_CST \
 245                                | OR_FCM_CHT \
 246                                | OR_FCM_SCY_1 \
 247                                | OR_FCM_TRLX \
 248                                | OR_FCM_EHTR)
 249
 250 #ifdef CONFIG_NAND
 251 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 252 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 253 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 254 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 255 #else
 256 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 257 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 258 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 259 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 260 #endif
 261 #else
 262 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 263 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 264 #endif /* CONFIG_NAND_FSL_ELBC */
 265
 266 #define CONFIG_SYS_FLASH_EMPTY_INFO
 267 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 268 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 269
 270 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 271 #define CONFIG_MISC_INIT_R
 272
 273 #define CONFIG_HWCONFIG
 274
 275 /* define to use L1 as initial stack */
 276 #define CONFIG_L1_INIT_RAM
 277 #define CONFIG_SYS_INIT_RAM_LOCK
 278 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 279 #ifdef CONFIG_PHYS_64BIT
 280 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 282 /* The assembler doesn't like typecast */
 283 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 284         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 285           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 286 #else
 287 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 290 #endif
 291 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 292
 293 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 294 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 295
 296 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 297 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 298
 299 /* Serial Port - controlled on board with jumper J8
 300  * open - index 2
 301  * shorted - index 1
 302  */
 303 #define CONFIG_SYS_NS16550_SERIAL
 304 #define CONFIG_SYS_NS16550_REG_SIZE     1
 305 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 306
 307 #define CONFIG_SYS_BAUDRATE_TABLE       \
 308         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 309
 310 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 311 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 312 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 313 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 314
 315 /* I2C */
 316 #define CONFIG_SYS_I2C
 317 #define CONFIG_SYS_I2C_FSL
 318 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 319 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 320 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 321 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 322 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 323 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 324
 325 /*
 326  * RapidIO
 327  */
 328 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 329 #ifdef CONFIG_PHYS_64BIT
 330 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 331 #else
 332 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 333 #endif
 334 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 335
 336 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 337 #ifdef CONFIG_PHYS_64BIT
 338 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 339 #else
 340 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 341 #endif
 342 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 343
 344 /*
 345  * for slave u-boot IMAGE instored in master memory space,
 346  * PHYS must be aligned based on the SIZE
 347  */
 348 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 352 /*
 353  * for slave UCODE and ENV instored in master memory space,
 354  * PHYS must be aligned based on the SIZE
 355  */
 356 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 357 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 359
 360 /* slave core release by master*/
 361 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 362 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 363
 364 /*
 365  * SRIO_PCIE_BOOT - SLAVE
 366  */
 367 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 368 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 369 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 370                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 371 #endif
 372
 373 /*
 374  * eSPI - Enhanced SPI
 375  */
 376 #define CONFIG_SF_DEFAULT_SPEED         10000000
 377 #define CONFIG_SF_DEFAULT_MODE          0
 378
 379 /*
 380  * General PCI
 381  * Memory space is mapped 1-1, but I/O space must start from 0.
 382  */
 383
 384 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 385 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 386 #ifdef CONFIG_PHYS_64BIT
 387 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 388 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 389 #else
 390 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 391 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 392 #endif
 393 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 394 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 395 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 396 #ifdef CONFIG_PHYS_64BIT
 397 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 398 #else
 399 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 400 #endif
 401 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 402
 403 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 404 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 405 #ifdef CONFIG_PHYS_64BIT
 406 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 407 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 408 #else
 409 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 410 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 411 #endif
 412 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 413 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 414 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 415 #ifdef CONFIG_PHYS_64BIT
 416 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 417 #else
 418 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 419 #endif
 420 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 421
 422 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 423 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 424 #ifdef CONFIG_PHYS_64BIT
 425 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 426 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 427 #else
 428 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 429 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 430 #endif
 431 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 432 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 433 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 434 #ifdef CONFIG_PHYS_64BIT
 435 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 436 #else
 437 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 438 #endif
 439 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 440
 441 /* controller 4, Base address 203000 */
 442 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 443 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 444 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 445 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 446 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 447 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 448
 449 /* Qman/Bman */
 450 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 451 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 452 #ifdef CONFIG_PHYS_64BIT
 453 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 454 #else
 455 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 456 #endif
 457 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 458 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 459 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 460 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 461 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 462 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 463                                         CONFIG_SYS_BMAN_CENA_SIZE)
 464 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 465 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 466 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 467 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 468 #ifdef CONFIG_PHYS_64BIT
 469 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 470 #else
 471 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 472 #endif
 473 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 474 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 475 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 476 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 477 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 478 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 479                                         CONFIG_SYS_QMAN_CENA_SIZE)
 480 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 481 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 482
 483 #define CONFIG_SYS_DPAA_FMAN
 484 #define CONFIG_SYS_DPAA_PME
 485 /* Default address of microcode for the Linux Fman driver */
 486 #if defined(CONFIG_SPIFLASH)
 487 /*
 488  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 489  * env, so we got 0x110000.
 490  */
 491 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 492 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 493 #elif defined(CONFIG_SDCARD)
 494 /*
 495  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 496  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 497  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 498  */
 499 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 500 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 501 #elif defined(CONFIG_NAND)
 502 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 503 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 504 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 505 /*
 506  * Slave has no ucode locally, it can fetch this from remote. When implementing
 507  * in two corenet boards, slave's ucode could be stored in master's memory
 508  * space, the address can be mapped from slave TLB->slave LAW->
 509  * slave SRIO or PCIE outbound window->master inbound window->
 510  * master LAW->the ucode address in master's memory space.
 511  */
 512 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 513 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 514 #else
 515 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 516 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 517 #endif
 518 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 519 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 520
 521 #ifdef CONFIG_SYS_DPAA_FMAN
 522 #define CONFIG_FMAN_ENET
 523 #define CONFIG_PHYLIB_10G
 524 #define CONFIG_PHY_VITESSE
 525 #define CONFIG_PHY_TERANETICS
 526 #endif
 527
 528 #ifdef CONFIG_PCI
 529 #define CONFIG_PCI_INDIRECT_BRIDGE
 530
 531 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 532 #endif  /* CONFIG_PCI */
 533
 534 /* SATA */
 535 #ifdef CONFIG_FSL_SATA_V2
 536 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 537 #define CONFIG_SATA1
 538 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 539 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 540 #define CONFIG_SATA2
 541 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 542 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 543
 544 #define CONFIG_LBA48
 545 #endif
 546
 547 #ifdef CONFIG_FMAN_ENET
 548 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 549 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 550 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 551 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 552 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 553
 554 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 555 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 556 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 557 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 558 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 559
 560 #define CONFIG_SYS_TBIPA_VALUE  8
 561 #define CONFIG_MII              /* MII PHY management */
 562 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 563 #endif
 564
 565 /*
 566  * Environment
 567  */
 568 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 569 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 570
 571 /*
 572 * USB
 573 */
 574 #define CONFIG_HAS_FSL_DR_USB
 575 #define CONFIG_HAS_FSL_MPH_USB
 576
 577 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 578 #define CONFIG_USB_EHCI_FSL
 579 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 580 #endif
 581
 582 #ifdef CONFIG_MMC
 583 #define CONFIG_FSL_ESDHC
 584 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 585 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 586 #endif
 587
 588 /*
 589  * Miscellaneous configurable options
 590  */
 591 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 592
 593 /*
 594  * For booting Linux, the board info and command line data
 595  * have to be in the first 64 MB of memory, since this is
 596  * the maximum mapped by the Linux kernel during initialization.
 597  */
 598 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 599 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 600
 601 #ifdef CONFIG_CMD_KGDB
 602 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 603 #endif
 604
 605 /*
 606  * Environment Configuration
 607  */
 608 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 609 #define CONFIG_BOOTFILE         "uImage"
 610 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 611
 612 /* default location for tftp and bootm */
 613 #define CONFIG_LOADADDR         1000000
 614
 615 #ifdef CONFIG_TARGET_P4080DS
 616 #define __USB_PHY_TYPE  ulpi
 617 #else
 618 #define __USB_PHY_TYPE  utmi
 619 #endif
 620
 621 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 622         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 623         "bank_intlv=cs0_cs1;"                                   \
 624         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 625         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 626         "netdev=eth0\0"                                         \
 627         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 628         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 629         "tftpflash=tftpboot $loadaddr $uboot && "               \
 630         "protect off $ubootaddr +$filesize && "                 \
 631         "erase $ubootaddr +$filesize && "                       \
 632         "cp.b $loadaddr $ubootaddr $filesize && "               \
 633         "protect on $ubootaddr +$filesize && "                  \
 634         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 635         "consoledev=ttyS0\0"                                    \
 636         "ramdiskaddr=2000000\0"                                 \
 637         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 638         "fdtaddr=1e00000\0"                                     \
 639         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 640         "bdev=sda3\0"
 641
 642 #define CONFIG_HDBOOT                                   \
 643         "setenv bootargs root=/dev/$bdev rw "           \
 644         "console=$consoledev,$baudrate $othbootargs;"   \
 645         "tftp $loadaddr $bootfile;"                     \
 646         "tftp $fdtaddr $fdtfile;"                       \
 647         "bootm $loadaddr - $fdtaddr"
 648
 649 #define CONFIG_NFSBOOTCOMMAND                   \
 650         "setenv bootargs root=/dev/nfs rw "     \
 651         "nfsroot=$serverip:$rootpath "          \
 652         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 653         "console=$consoledev,$baudrate $othbootargs;"   \
 654         "tftp $loadaddr $bootfile;"             \
 655         "tftp $fdtaddr $fdtfile;"               \
 656         "bootm $loadaddr - $fdtaddr"
 657
 658 #define CONFIG_RAMBOOTCOMMAND                           \
 659         "setenv bootargs root=/dev/ram rw "             \
 660         "console=$consoledev,$baudrate $othbootargs;"   \
 661         "tftp $ramdiskaddr $ramdiskfile;"               \
 662         "tftp $loadaddr $bootfile;"                     \
 663         "tftp $fdtaddr $fdtfile;"                       \
 664         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 665
 666 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 667
 668 #include <asm/fsl_secure_boot.h>
 669
 670 #endif  /* __CONFIG_H */