include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #include "../board/freescale/common/ics307_clk.h"
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  19 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  20 #endif
  21
  22 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  23 /* Set 1M boot space */
  24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  25 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  26                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  28 #endif
  29
  30 /* High Level Configuration Options */
  31 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  32
  33 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  34 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  35 #endif
  36
  37 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  38 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  39 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  40 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  41
  42 /*
  43  * These can be toggled for performance analysis, otherwise use default.
  44  */
  45 #define CONFIG_SYS_CACHE_STASHING
  46 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  47 #ifdef CONFIG_DDR_ECC
  48 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  49 #endif
  50
  51 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  52
  53 /*
  54  *  Config the L3 Cache as L3 SRAM
  55  */
  56 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  57 #ifdef CONFIG_PHYS_64BIT
  58 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  59 #else
  60 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  61 #endif
  62 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  63 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  64
  65 #ifdef CONFIG_PHYS_64BIT
  66 #define CONFIG_SYS_DCSRBAR              0xf0000000
  67 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  68 #endif
  69
  70 /* EEPROM */
  71 #define CONFIG_SYS_I2C_EEPROM_NXID
  72 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  73
  74 /*
  75  * DDR Setup
  76  */
  77 #define CONFIG_VERY_BIG_RAM
  78 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  79 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  80
  81 #define SPD_EEPROM_ADDRESS1     0x51
  82 #define SPD_EEPROM_ADDRESS2     0x52
  83 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
  84 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  85
  86 /*
  87  * Local Bus Definitions
  88  */
  89
  90 /* Set the local bus clock 1/8 of platform clock */
  91 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  92
  93 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
  94 #ifdef CONFIG_PHYS_64BIT
  95 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
  96 #else
  97 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  98 #endif
  99
 100 #define CONFIG_SYS_FLASH_BR_PRELIM \
 101                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 102                  | BR_PS_16 | BR_V)
 103 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 104                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 105
 106 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 107 #ifdef CONFIG_PHYS_64BIT
 108 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 109 #else
 110 #define PIXIS_BASE_PHYS         PIXIS_BASE
 111 #endif
 112
 113 #define PIXIS_LBMAP_SWITCH      7
 114 #define PIXIS_LBMAP_MASK        0xf0
 115 #define PIXIS_LBMAP_SHIFT       4
 116 #define PIXIS_LBMAP_ALTBANK     0x40
 117
 118 #define CONFIG_SYS_FLASH_QUIET_TEST
 119 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 120
 121 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 122 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 123 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 124
 125 #if defined(CONFIG_RAMBOOT_PBL)
 126 #define CONFIG_SYS_RAMBOOT
 127 #endif
 128
 129 /* Nand Flash */
 130 #ifdef CONFIG_NAND_FSL_ELBC
 131 #define CONFIG_SYS_NAND_BASE            0xffa00000
 132 #ifdef CONFIG_PHYS_64BIT
 133 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 134 #else
 135 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 136 #endif
 137
 138 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 139 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 140
 141 /* NAND flash config */
 142 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 143                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 144                                | BR_PS_8               /* Port Size = 8 bit */ \
 145                                | BR_MS_FCM             /* MSEL = FCM */ \
 146                                | BR_V)                 /* valid */
 147 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 148                                | OR_FCM_PGS            /* Large Page*/ \
 149                                | OR_FCM_CSCT \
 150                                | OR_FCM_CST \
 151                                | OR_FCM_CHT \
 152                                | OR_FCM_SCY_1 \
 153                                | OR_FCM_TRLX \
 154                                | OR_FCM_EHTR)
 155 #endif /* CONFIG_NAND_FSL_ELBC */
 156
 157 #define CONFIG_SYS_FLASH_EMPTY_INFO
 158 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 159
 160 #define CONFIG_HWCONFIG
 161
 162 /* define to use L1 as initial stack */
 163 #define CONFIG_L1_INIT_RAM
 164 #define CONFIG_SYS_INIT_RAM_LOCK
 165 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 166 #ifdef CONFIG_PHYS_64BIT
 167 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 168 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 169 /* The assembler doesn't like typecast */
 170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 171         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 172           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 173 #else
 174 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 175 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 176 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 177 #endif
 178 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 179
 180 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 181
 182 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 183
 184 /* Serial Port - controlled on board with jumper J8
 185  * open - index 2
 186  * shorted - index 1
 187  */
 188 #define CONFIG_SYS_NS16550_SERIAL
 189 #define CONFIG_SYS_NS16550_REG_SIZE     1
 190 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 191
 192 #define CONFIG_SYS_BAUDRATE_TABLE       \
 193         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 194
 195 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 196 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 197 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 198 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 199
 200 /* I2C */
 201
 202 /*
 203  * RapidIO
 204  */
 205 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 206 #ifdef CONFIG_PHYS_64BIT
 207 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 208 #else
 209 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 210 #endif
 211 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 212
 213 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 214 #ifdef CONFIG_PHYS_64BIT
 215 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 216 #else
 217 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 218 #endif
 219 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 220
 221 /*
 222  * for slave u-boot IMAGE instored in master memory space,
 223  * PHYS must be aligned based on the SIZE
 224  */
 225 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 226 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 227 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 228 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 229 /*
 230  * for slave UCODE and ENV instored in master memory space,
 231  * PHYS must be aligned based on the SIZE
 232  */
 233 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 234 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 235 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 236
 237 /* slave core release by master*/
 238 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 239 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 240
 241 /*
 242  * SRIO_PCIE_BOOT - SLAVE
 243  */
 244 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 245 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 246 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 247                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 248 #endif
 249
 250 /*
 251  * eSPI - Enhanced SPI
 252  */
 253
 254 /*
 255  * General PCI
 256  * Memory space is mapped 1-1, but I/O space must start from 0.
 257  */
 258
 259 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 260 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 261 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 262 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 263 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 264
 265 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 266 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 267 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 268 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 269 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 270
 271 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 272 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 273 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 274 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 275 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 276
 277 /* controller 4, Base address 203000 */
 278 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 279 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 280
 281 /* Qman/Bman */
 282 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 283 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 284 #ifdef CONFIG_PHYS_64BIT
 285 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 286 #else
 287 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 288 #endif
 289 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 290 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 291 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 292 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 293 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 294 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 295                                         CONFIG_SYS_BMAN_CENA_SIZE)
 296 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 297 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 298 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 299 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 300 #ifdef CONFIG_PHYS_64BIT
 301 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 302 #else
 303 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 304 #endif
 305 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 306 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 307 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 308 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 309 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 310 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 311                                         CONFIG_SYS_QMAN_CENA_SIZE)
 312 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 313 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 314
 315 #define CONFIG_SYS_DPAA_FMAN
 316 #define CONFIG_SYS_DPAA_PME
 317 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 318
 319 #ifdef CONFIG_PCI
 320 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 321 #endif  /* CONFIG_PCI */
 322
 323 #ifdef CONFIG_FMAN_ENET
 324 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 325 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 326 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 327 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 328 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 329
 330 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 331 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 332 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 333 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 334 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 335
 336 #define CONFIG_SYS_TBIPA_VALUE  8
 337 #endif
 338
 339 /*
 340  * Environment
 341  */
 342 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 343 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 344
 345 #ifdef CONFIG_MMC
 346 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 347 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 348 #endif
 349
 350 /*
 351  * Miscellaneous configurable options
 352  */
 353
 354 /*
 355  * For booting Linux, the board info and command line data
 356  * have to be in the first 64 MB of memory, since this is
 357  * the maximum mapped by the Linux kernel during initialization.
 358  */
 359 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 360 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 361
 362 /*
 363  * Environment Configuration
 364  */
 365 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 366 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 367
 368 #ifdef CONFIG_TARGET_P4080DS
 369 #define __USB_PHY_TYPE  ulpi
 370 #else
 371 #define __USB_PHY_TYPE  utmi
 372 #endif
 373
 374 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 375         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 376         "bank_intlv=cs0_cs1;"                                   \
 377         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 378         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 379         "netdev=eth0\0"                                         \
 380         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 381         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 382         "tftpflash=tftpboot $loadaddr $uboot && "               \
 383         "protect off $ubootaddr +$filesize && "                 \
 384         "erase $ubootaddr +$filesize && "                       \
 385         "cp.b $loadaddr $ubootaddr $filesize && "               \
 386         "protect on $ubootaddr +$filesize && "                  \
 387         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 388         "consoledev=ttyS0\0"                                    \
 389         "ramdiskaddr=2000000\0"                                 \
 390         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 391         "fdtaddr=1e00000\0"                                     \
 392         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 393         "bdev=sda3\0"
 394
 395 #include <asm/fsl_secure_boot.h>
 396
 397 #endif  /* __CONFIG_H */