1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * Corenet DS style board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
17 #ifdef CONFIG_RAMBOOT_PBL
18 #ifdef CONFIG_NXP_ESBC
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21 #ifdef CONFIG_MTD_RAW_NAND
22 #define CONFIG_RAMBOOT_NAND
24 #define CONFIG_BOOTSCRIPT_COPY_RAM
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
31 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
32 /* Set 1M boot space */
33 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
34 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
35 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
39 /* High Level Configuration Options */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
42 #ifndef CONFIG_RESET_VECTOR_ADDRESS
43 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
46 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
47 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
48 #define CONFIG_PCIE1 /* PCIE controller 1 */
49 #define CONFIG_PCIE2 /* PCIE controller 2 */
51 #if defined(CONFIG_SPIFLASH)
52 #elif defined(CONFIG_SDCARD)
53 #define CONFIG_FSL_FIXED_MMC_LOCATION
57 * These can be toggled for performance analysis, otherwise use default.
59 #define CONFIG_SYS_CACHE_STASHING
60 #define CONFIG_BACKSIDE_L2_CACHE
61 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
62 #define CONFIG_BTB /* toggle branch predition */
64 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
67 #define CONFIG_ENABLE_36BIT_PHYS
69 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
72 * Config the L3 Cache as L3 SRAM
74 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
75 #ifdef CONFIG_PHYS_64BIT
76 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
78 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
80 #define CONFIG_SYS_L3_SIZE (1024 << 10)
81 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
83 #ifdef CONFIG_PHYS_64BIT
84 #define CONFIG_SYS_DCSRBAR 0xf0000000
85 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
89 #define CONFIG_SYS_I2C_EEPROM_NXID
90 #define CONFIG_SYS_EEPROM_BUS_NUM 0
95 #define CONFIG_VERY_BIG_RAM
96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
99 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
100 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
102 #define CONFIG_SYS_SPD_BUS_NUM 1
103 #define SPD_EEPROM_ADDRESS1 0x51
104 #define SPD_EEPROM_ADDRESS2 0x52
105 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
106 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
109 * Local Bus Definitions
112 /* Set the local bus clock 1/8 of platform clock */
113 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
115 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
116 #ifdef CONFIG_PHYS_64BIT
117 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
119 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
122 #define CONFIG_SYS_FLASH_BR_PRELIM \
123 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
125 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
126 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
128 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
129 #ifdef CONFIG_PHYS_64BIT
130 #define PIXIS_BASE_PHYS 0xfffdf0000ull
132 #define PIXIS_BASE_PHYS PIXIS_BASE
135 #define PIXIS_LBMAP_SWITCH 7
136 #define PIXIS_LBMAP_MASK 0xf0
137 #define PIXIS_LBMAP_SHIFT 4
138 #define PIXIS_LBMAP_ALTBANK 0x40
140 #define CONFIG_SYS_FLASH_QUIET_TEST
141 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
143 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
144 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
145 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
147 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
149 #if defined(CONFIG_RAMBOOT_PBL)
150 #define CONFIG_SYS_RAMBOOT
154 #ifdef CONFIG_NAND_FSL_ELBC
155 #define CONFIG_SYS_NAND_BASE 0xffa00000
156 #ifdef CONFIG_PHYS_64BIT
157 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
159 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
162 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
163 #define CONFIG_SYS_MAX_NAND_DEVICE 1
165 /* NAND flash config */
166 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
167 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
168 | BR_PS_8 /* Port Size = 8 bit */ \
169 | BR_MS_FCM /* MSEL = FCM */ \
171 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
172 | OR_FCM_PGS /* Large Page*/ \
179 #endif /* CONFIG_NAND_FSL_ELBC */
181 #define CONFIG_SYS_FLASH_EMPTY_INFO
182 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
184 #define CONFIG_HWCONFIG
186 /* define to use L1 as initial stack */
187 #define CONFIG_L1_INIT_RAM
188 #define CONFIG_SYS_INIT_RAM_LOCK
189 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
190 #ifdef CONFIG_PHYS_64BIT
191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
192 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
193 /* The assembler doesn't like typecast */
194 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
195 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
196 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
199 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
200 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
202 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
204 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
205 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
207 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
209 /* Serial Port - controlled on board with jumper J8
213 #define CONFIG_SYS_NS16550_SERIAL
214 #define CONFIG_SYS_NS16550_REG_SIZE 1
215 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
217 #define CONFIG_SYS_BAUDRATE_TABLE \
218 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
220 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
221 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
222 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
223 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
230 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
231 #ifdef CONFIG_PHYS_64BIT
232 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
234 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
236 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
238 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
239 #ifdef CONFIG_PHYS_64BIT
240 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
242 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
244 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
247 * for slave u-boot IMAGE instored in master memory space,
248 * PHYS must be aligned based on the SIZE
250 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
251 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
252 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
253 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
255 * for slave UCODE and ENV instored in master memory space,
256 * PHYS must be aligned based on the SIZE
258 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
259 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
260 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
262 /* slave core release by master*/
263 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
264 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
267 * SRIO_PCIE_BOOT - SLAVE
269 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
270 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
271 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
272 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
276 * eSPI - Enhanced SPI
281 * Memory space is mapped 1-1, but I/O space must start from 0.
284 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
285 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
286 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
287 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
288 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
290 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
291 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
292 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
293 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
294 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
296 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
297 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
298 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
299 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
300 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
302 /* controller 4, Base address 203000 */
303 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
304 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
307 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
308 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
309 #ifdef CONFIG_PHYS_64BIT
310 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
312 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
314 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
315 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
316 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
317 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
318 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
319 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
320 CONFIG_SYS_BMAN_CENA_SIZE)
321 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
322 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
323 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
324 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
325 #ifdef CONFIG_PHYS_64BIT
326 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
328 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
330 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
331 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
332 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
333 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
334 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
335 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
336 CONFIG_SYS_QMAN_CENA_SIZE)
337 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
338 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
340 #define CONFIG_SYS_DPAA_FMAN
341 #define CONFIG_SYS_DPAA_PME
342 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
345 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
346 #endif /* CONFIG_PCI */
349 #ifdef CONFIG_FSL_SATA_V2
351 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
352 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
354 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
355 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
360 #ifdef CONFIG_FMAN_ENET
361 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
362 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
363 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
364 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
365 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
367 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
368 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
369 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
370 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
371 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
373 #define CONFIG_SYS_TBIPA_VALUE 8
374 #define CONFIG_ETHPRIME "FM1@DTSEC1"
380 #define CONFIG_LOADS_ECHO /* echo on for serial download */
381 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
386 #define CONFIG_HAS_FSL_DR_USB
387 #define CONFIG_HAS_FSL_MPH_USB
389 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
390 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
394 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
395 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
399 * Miscellaneous configurable options
403 * For booting Linux, the board info and command line data
404 * have to be in the first 64 MB of memory, since this is
405 * the maximum mapped by the Linux kernel during initialization.
407 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
408 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
411 * Environment Configuration
413 #define CONFIG_ROOTPATH "/opt/nfsroot"
414 #define CONFIG_BOOTFILE "uImage"
415 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
417 #ifdef CONFIG_TARGET_P4080DS
418 #define __USB_PHY_TYPE ulpi
420 #define __USB_PHY_TYPE utmi
423 #define CONFIG_EXTRA_ENV_SETTINGS \
424 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
425 "bank_intlv=cs0_cs1;" \
426 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
427 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
429 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
430 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
431 "tftpflash=tftpboot $loadaddr $uboot && " \
432 "protect off $ubootaddr +$filesize && " \
433 "erase $ubootaddr +$filesize && " \
434 "cp.b $loadaddr $ubootaddr $filesize && " \
435 "protect on $ubootaddr +$filesize && " \
436 "cmp.b $loadaddr $ubootaddr $filesize\0" \
437 "consoledev=ttyS0\0" \
438 "ramdiskaddr=2000000\0" \
439 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
440 "fdtaddr=1e00000\0" \
441 "fdtfile=p4080ds/p4080ds.dtb\0" \
444 #include <asm/fsl_secure_boot.h>
446 #endif /* __CONFIG_H */