1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * Corenet DS style board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
17 #ifdef CONFIG_RAMBOOT_PBL
18 #ifdef CONFIG_NXP_ESBC
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21 #ifdef CONFIG_MTD_RAW_NAND
22 #define CONFIG_RAMBOOT_NAND
24 #define CONFIG_BOOTSCRIPT_COPY_RAM
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
31 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
32 /* Set 1M boot space */
33 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
34 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
35 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
39 /* High Level Configuration Options */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
42 #ifndef CONFIG_RESET_VECTOR_ADDRESS
43 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
46 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
47 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
48 #define CONFIG_PCIE1 /* PCIE controller 1 */
49 #define CONFIG_PCIE2 /* PCIE controller 2 */
50 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
52 #if defined(CONFIG_SPIFLASH)
53 #elif defined(CONFIG_SDCARD)
54 #define CONFIG_FSL_FIXED_MMC_LOCATION
57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
60 * These can be toggled for performance analysis, otherwise use default.
62 #define CONFIG_SYS_CACHE_STASHING
63 #define CONFIG_BACKSIDE_L2_CACHE
64 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
65 #define CONFIG_BTB /* toggle branch predition */
67 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
70 #define CONFIG_ENABLE_36BIT_PHYS
72 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
75 * Config the L3 Cache as L3 SRAM
77 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
78 #ifdef CONFIG_PHYS_64BIT
79 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
81 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
83 #define CONFIG_SYS_L3_SIZE (1024 << 10)
84 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
86 #ifdef CONFIG_PHYS_64BIT
87 #define CONFIG_SYS_DCSRBAR 0xf0000000
88 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
92 #define CONFIG_SYS_I2C_EEPROM_NXID
93 #define CONFIG_SYS_EEPROM_BUS_NUM 0
98 #define CONFIG_VERY_BIG_RAM
99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
102 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
103 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
105 #define CONFIG_SYS_SPD_BUS_NUM 1
106 #define SPD_EEPROM_ADDRESS1 0x51
107 #define SPD_EEPROM_ADDRESS2 0x52
108 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
109 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
112 * Local Bus Definitions
115 /* Set the local bus clock 1/8 of platform clock */
116 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
118 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
119 #ifdef CONFIG_PHYS_64BIT
120 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
122 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
125 #define CONFIG_SYS_FLASH_BR_PRELIM \
126 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
128 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
129 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
131 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
132 #ifdef CONFIG_PHYS_64BIT
133 #define PIXIS_BASE_PHYS 0xfffdf0000ull
135 #define PIXIS_BASE_PHYS PIXIS_BASE
138 #define PIXIS_LBMAP_SWITCH 7
139 #define PIXIS_LBMAP_MASK 0xf0
140 #define PIXIS_LBMAP_SHIFT 4
141 #define PIXIS_LBMAP_ALTBANK 0x40
143 #define CONFIG_SYS_FLASH_QUIET_TEST
144 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
146 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
147 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
148 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
149 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
153 #if defined(CONFIG_RAMBOOT_PBL)
154 #define CONFIG_SYS_RAMBOOT
158 #ifdef CONFIG_NAND_FSL_ELBC
159 #define CONFIG_SYS_NAND_BASE 0xffa00000
160 #ifdef CONFIG_PHYS_64BIT
161 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
163 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
166 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
167 #define CONFIG_SYS_MAX_NAND_DEVICE 1
169 /* NAND flash config */
170 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
171 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
172 | BR_PS_8 /* Port Size = 8 bit */ \
173 | BR_MS_FCM /* MSEL = FCM */ \
175 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
176 | OR_FCM_PGS /* Large Page*/ \
183 #endif /* CONFIG_NAND_FSL_ELBC */
185 #define CONFIG_SYS_FLASH_EMPTY_INFO
186 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
188 #define CONFIG_HWCONFIG
190 /* define to use L1 as initial stack */
191 #define CONFIG_L1_INIT_RAM
192 #define CONFIG_SYS_INIT_RAM_LOCK
193 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
194 #ifdef CONFIG_PHYS_64BIT
195 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
197 /* The assembler doesn't like typecast */
198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
199 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
200 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
202 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
203 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
204 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
206 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
208 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
209 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
211 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
213 /* Serial Port - controlled on board with jumper J8
217 #define CONFIG_SYS_NS16550_SERIAL
218 #define CONFIG_SYS_NS16550_REG_SIZE 1
219 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
221 #define CONFIG_SYS_BAUDRATE_TABLE \
222 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
224 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
225 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
226 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
227 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
234 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
235 #ifdef CONFIG_PHYS_64BIT
236 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
238 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
240 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
242 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
243 #ifdef CONFIG_PHYS_64BIT
244 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
246 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
248 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
251 * for slave u-boot IMAGE instored in master memory space,
252 * PHYS must be aligned based on the SIZE
254 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
255 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
256 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
257 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
259 * for slave UCODE and ENV instored in master memory space,
260 * PHYS must be aligned based on the SIZE
262 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
263 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
264 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
266 /* slave core release by master*/
267 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
268 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
271 * SRIO_PCIE_BOOT - SLAVE
273 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
274 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
275 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
276 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
280 * eSPI - Enhanced SPI
285 * Memory space is mapped 1-1, but I/O space must start from 0.
288 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
289 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
290 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
291 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
292 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
294 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
295 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
296 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
297 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
298 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
300 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
301 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
302 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
303 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
304 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
306 /* controller 4, Base address 203000 */
307 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
308 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
311 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
312 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
313 #ifdef CONFIG_PHYS_64BIT
314 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
316 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
318 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
319 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
320 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
321 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
322 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
323 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
324 CONFIG_SYS_BMAN_CENA_SIZE)
325 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
326 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
327 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
328 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
329 #ifdef CONFIG_PHYS_64BIT
330 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
332 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
334 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
335 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
336 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
337 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
338 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
339 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
340 CONFIG_SYS_QMAN_CENA_SIZE)
341 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
342 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
344 #define CONFIG_SYS_DPAA_FMAN
345 #define CONFIG_SYS_DPAA_PME
346 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
349 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
350 #endif /* CONFIG_PCI */
353 #ifdef CONFIG_FSL_SATA_V2
354 #define CONFIG_SYS_SATA_MAX_DEVICE 2
356 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
357 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
359 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
360 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
365 #ifdef CONFIG_FMAN_ENET
366 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
367 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
368 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
369 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
370 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
372 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
373 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
374 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
375 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
376 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
378 #define CONFIG_SYS_TBIPA_VALUE 8
379 #define CONFIG_ETHPRIME "FM1@DTSEC1"
385 #define CONFIG_LOADS_ECHO /* echo on for serial download */
386 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
391 #define CONFIG_HAS_FSL_DR_USB
392 #define CONFIG_HAS_FSL_MPH_USB
394 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
395 #define CONFIG_USB_EHCI_FSL
396 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
400 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
401 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
405 * Miscellaneous configurable options
409 * For booting Linux, the board info and command line data
410 * have to be in the first 64 MB of memory, since this is
411 * the maximum mapped by the Linux kernel during initialization.
413 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
414 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
417 * Environment Configuration
419 #define CONFIG_ROOTPATH "/opt/nfsroot"
420 #define CONFIG_BOOTFILE "uImage"
421 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
423 #ifdef CONFIG_TARGET_P4080DS
424 #define __USB_PHY_TYPE ulpi
426 #define __USB_PHY_TYPE utmi
429 #define CONFIG_EXTRA_ENV_SETTINGS \
430 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
431 "bank_intlv=cs0_cs1;" \
432 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
433 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
435 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
436 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
437 "tftpflash=tftpboot $loadaddr $uboot && " \
438 "protect off $ubootaddr +$filesize && " \
439 "erase $ubootaddr +$filesize && " \
440 "cp.b $loadaddr $ubootaddr $filesize && " \
441 "protect on $ubootaddr +$filesize && " \
442 "cmp.b $loadaddr $ubootaddr $filesize\0" \
443 "consoledev=ttyS0\0" \
444 "ramdiskaddr=2000000\0" \
445 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
446 "fdtaddr=1e00000\0" \
447 "fdtfile=p4080ds/p4080ds.dtb\0" \
450 #include <asm/fsl_secure_boot.h>
452 #endif /* __CONFIG_H */