1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * Corenet DS style board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
17 #ifdef CONFIG_RAMBOOT_PBL
18 #ifdef CONFIG_NXP_ESBC
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21 #ifdef CONFIG_MTD_RAW_NAND
22 #define CONFIG_RAMBOOT_NAND
24 #define CONFIG_BOOTSCRIPT_COPY_RAM
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
31 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
32 /* Set 1M boot space */
33 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
34 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
35 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
39 /* High Level Configuration Options */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
42 #ifndef CONFIG_RESET_VECTOR_ADDRESS
43 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
46 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
47 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
48 #define CONFIG_PCIE1 /* PCIE controller 1 */
49 #define CONFIG_PCIE2 /* PCIE controller 2 */
51 #if defined(CONFIG_SPIFLASH)
52 #elif defined(CONFIG_SDCARD)
53 #define CONFIG_FSL_FIXED_MMC_LOCATION
57 * These can be toggled for performance analysis, otherwise use default.
59 #define CONFIG_SYS_CACHE_STASHING
60 #define CONFIG_BACKSIDE_L2_CACHE
61 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
63 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
66 #define CONFIG_ENABLE_36BIT_PHYS
68 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
71 * Config the L3 Cache as L3 SRAM
73 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
74 #ifdef CONFIG_PHYS_64BIT
75 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
77 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
79 #define CONFIG_SYS_L3_SIZE (1024 << 10)
80 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
82 #ifdef CONFIG_PHYS_64BIT
83 #define CONFIG_SYS_DCSRBAR 0xf0000000
84 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
88 #define CONFIG_SYS_I2C_EEPROM_NXID
89 #define CONFIG_SYS_EEPROM_BUS_NUM 0
94 #define CONFIG_VERY_BIG_RAM
95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
99 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
101 #define CONFIG_SYS_SPD_BUS_NUM 1
102 #define SPD_EEPROM_ADDRESS1 0x51
103 #define SPD_EEPROM_ADDRESS2 0x52
104 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
105 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
108 * Local Bus Definitions
111 /* Set the local bus clock 1/8 of platform clock */
112 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
114 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
115 #ifdef CONFIG_PHYS_64BIT
116 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
118 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
121 #define CONFIG_SYS_FLASH_BR_PRELIM \
122 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
124 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
125 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
127 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
128 #ifdef CONFIG_PHYS_64BIT
129 #define PIXIS_BASE_PHYS 0xfffdf0000ull
131 #define PIXIS_BASE_PHYS PIXIS_BASE
134 #define PIXIS_LBMAP_SWITCH 7
135 #define PIXIS_LBMAP_MASK 0xf0
136 #define PIXIS_LBMAP_SHIFT 4
137 #define PIXIS_LBMAP_ALTBANK 0x40
139 #define CONFIG_SYS_FLASH_QUIET_TEST
140 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
142 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
143 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
144 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
148 #if defined(CONFIG_RAMBOOT_PBL)
149 #define CONFIG_SYS_RAMBOOT
153 #ifdef CONFIG_NAND_FSL_ELBC
154 #define CONFIG_SYS_NAND_BASE 0xffa00000
155 #ifdef CONFIG_PHYS_64BIT
156 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
158 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
161 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
162 #define CONFIG_SYS_MAX_NAND_DEVICE 1
164 /* NAND flash config */
165 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
166 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
167 | BR_PS_8 /* Port Size = 8 bit */ \
168 | BR_MS_FCM /* MSEL = FCM */ \
170 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
171 | OR_FCM_PGS /* Large Page*/ \
178 #endif /* CONFIG_NAND_FSL_ELBC */
180 #define CONFIG_SYS_FLASH_EMPTY_INFO
181 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
183 #define CONFIG_HWCONFIG
185 /* define to use L1 as initial stack */
186 #define CONFIG_L1_INIT_RAM
187 #define CONFIG_SYS_INIT_RAM_LOCK
188 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
189 #ifdef CONFIG_PHYS_64BIT
190 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
192 /* The assembler doesn't like typecast */
193 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
194 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
195 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
199 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
201 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
203 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
204 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
206 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
208 /* Serial Port - controlled on board with jumper J8
212 #define CONFIG_SYS_NS16550_SERIAL
213 #define CONFIG_SYS_NS16550_REG_SIZE 1
214 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
216 #define CONFIG_SYS_BAUDRATE_TABLE \
217 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
219 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
220 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
221 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
222 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
229 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
230 #ifdef CONFIG_PHYS_64BIT
231 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
233 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
235 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
237 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
238 #ifdef CONFIG_PHYS_64BIT
239 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
241 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
243 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
246 * for slave u-boot IMAGE instored in master memory space,
247 * PHYS must be aligned based on the SIZE
249 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
250 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
251 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
252 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
254 * for slave UCODE and ENV instored in master memory space,
255 * PHYS must be aligned based on the SIZE
257 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
258 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
259 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
261 /* slave core release by master*/
262 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
263 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
266 * SRIO_PCIE_BOOT - SLAVE
268 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
269 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
270 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
271 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
275 * eSPI - Enhanced SPI
280 * Memory space is mapped 1-1, but I/O space must start from 0.
283 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
284 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
285 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
286 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
287 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
289 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
290 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
291 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
292 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
293 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
295 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
296 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
297 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
298 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
299 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
301 /* controller 4, Base address 203000 */
302 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
303 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
306 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
307 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
308 #ifdef CONFIG_PHYS_64BIT
309 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
311 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
313 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
314 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
315 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
316 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
317 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
318 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
319 CONFIG_SYS_BMAN_CENA_SIZE)
320 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
321 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
322 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
323 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
324 #ifdef CONFIG_PHYS_64BIT
325 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
327 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
329 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
330 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
331 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
332 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
333 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
334 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
335 CONFIG_SYS_QMAN_CENA_SIZE)
336 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
337 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
339 #define CONFIG_SYS_DPAA_FMAN
340 #define CONFIG_SYS_DPAA_PME
341 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
344 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
345 #endif /* CONFIG_PCI */
348 #ifdef CONFIG_FSL_SATA_V2
350 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
351 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
353 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
354 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
359 #ifdef CONFIG_FMAN_ENET
360 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
361 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
362 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
363 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
364 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
366 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
367 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
368 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
369 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
370 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
372 #define CONFIG_SYS_TBIPA_VALUE 8
373 #define CONFIG_ETHPRIME "FM1@DTSEC1"
379 #define CONFIG_LOADS_ECHO /* echo on for serial download */
380 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
385 #define CONFIG_HAS_FSL_DR_USB
386 #define CONFIG_HAS_FSL_MPH_USB
388 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
389 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
393 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
394 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
398 * Miscellaneous configurable options
402 * For booting Linux, the board info and command line data
403 * have to be in the first 64 MB of memory, since this is
404 * the maximum mapped by the Linux kernel during initialization.
406 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
407 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
410 * Environment Configuration
412 #define CONFIG_ROOTPATH "/opt/nfsroot"
413 #define CONFIG_BOOTFILE "uImage"
414 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
416 #ifdef CONFIG_TARGET_P4080DS
417 #define __USB_PHY_TYPE ulpi
419 #define __USB_PHY_TYPE utmi
422 #define CONFIG_EXTRA_ENV_SETTINGS \
423 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
424 "bank_intlv=cs0_cs1;" \
425 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
426 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
428 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
429 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
430 "tftpflash=tftpboot $loadaddr $uboot && " \
431 "protect off $ubootaddr +$filesize && " \
432 "erase $ubootaddr +$filesize && " \
433 "cp.b $loadaddr $ubootaddr $filesize && " \
434 "protect on $ubootaddr +$filesize && " \
435 "cmp.b $loadaddr $ubootaddr $filesize\0" \
436 "consoledev=ttyS0\0" \
437 "ramdiskaddr=2000000\0" \
438 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
439 "fdtaddr=1e00000\0" \
440 "fdtfile=p4080ds/p4080ds.dtb\0" \
443 #include <asm/fsl_secure_boot.h>
445 #endif /* __CONFIG_H */