include/configs/corenet_ds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #include <linux/stringify.h>
  14
  15 #include "../board/freescale/common/ics307_clk.h"
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #ifdef CONFIG_NXP_ESBC
  19 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  21 #ifdef CONFIG_MTD_RAW_NAND
  22 #define CONFIG_RAMBOOT_NAND
  23 #endif
  24 #define CONFIG_BOOTSCRIPT_COPY_RAM
  25 #else
  26 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  28 #endif
  29 #endif
  30
  31 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  32 /* Set 1M boot space */
  33 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  34 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  35                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  37 #endif
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  41
  42 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  43 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  44 #endif
  45
  46 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  47 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  48 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  49 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  50 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  51
  52 #if defined(CONFIG_SPIFLASH)
  53 #elif defined(CONFIG_SDCARD)
  54 #define CONFIG_FSL_FIXED_MMC_LOCATION
  55 #endif
  56
  57 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  58
  59 /*
  60  * These can be toggled for performance analysis, otherwise use default.
  61  */
  62 #define CONFIG_SYS_CACHE_STASHING
  63 #define CONFIG_BACKSIDE_L2_CACHE
  64 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  65 #define CONFIG_BTB                      /* toggle branch predition */
  66 #ifdef CONFIG_DDR_ECC
  67 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  68 #endif
  69
  70 #define CONFIG_ENABLE_36BIT_PHYS
  71
  72 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  73
  74 /*
  75  *  Config the L3 Cache as L3 SRAM
  76  */
  77 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  78 #ifdef CONFIG_PHYS_64BIT
  79 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  80 #else
  81 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  82 #endif
  83 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  84 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  85
  86 #ifdef CONFIG_PHYS_64BIT
  87 #define CONFIG_SYS_DCSRBAR              0xf0000000
  88 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  89 #endif
  90
  91 /* EEPROM */
  92 #define CONFIG_SYS_I2C_EEPROM_NXID
  93 #define CONFIG_SYS_EEPROM_BUS_NUM       0
  94
  95 /*
  96  * DDR Setup
  97  */
  98 #define CONFIG_VERY_BIG_RAM
  99 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 100 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 101
 102 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 103 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 104
 105 #define CONFIG_SYS_SPD_BUS_NUM  1
 106 #define SPD_EEPROM_ADDRESS1     0x51
 107 #define SPD_EEPROM_ADDRESS2     0x52
 108 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 109 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 110
 111 /*
 112  * Local Bus Definitions
 113  */
 114
 115 /* Set the local bus clock 1/8 of platform clock */
 116 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 117
 118 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 119 #ifdef CONFIG_PHYS_64BIT
 120 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 121 #else
 122 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 123 #endif
 124
 125 #define CONFIG_SYS_FLASH_BR_PRELIM \
 126                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 127                  | BR_PS_16 | BR_V)
 128 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 129                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 130
 131 #define CONFIG_SYS_BR1_PRELIM \
 132         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 133 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 134
 135 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 136 #ifdef CONFIG_PHYS_64BIT
 137 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 138 #else
 139 #define PIXIS_BASE_PHYS         PIXIS_BASE
 140 #endif
 141
 142 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 143 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 144
 145 #define PIXIS_LBMAP_SWITCH      7
 146 #define PIXIS_LBMAP_MASK        0xf0
 147 #define PIXIS_LBMAP_SHIFT       4
 148 #define PIXIS_LBMAP_ALTBANK     0x40
 149
 150 #define CONFIG_SYS_FLASH_QUIET_TEST
 151 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 152
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 154 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 155 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 156 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 157
 158 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 159
 160 #if defined(CONFIG_RAMBOOT_PBL)
 161 #define CONFIG_SYS_RAMBOOT
 162 #endif
 163
 164 /* Nand Flash */
 165 #ifdef CONFIG_NAND_FSL_ELBC
 166 #define CONFIG_SYS_NAND_BASE            0xffa00000
 167 #ifdef CONFIG_PHYS_64BIT
 168 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 169 #else
 170 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 171 #endif
 172
 173 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 174 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 175
 176 /* NAND flash config */
 177 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 178                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 179                                | BR_PS_8               /* Port Size = 8 bit */ \
 180                                | BR_MS_FCM             /* MSEL = FCM */ \
 181                                | BR_V)                 /* valid */
 182 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 183                                | OR_FCM_PGS            /* Large Page*/ \
 184                                | OR_FCM_CSCT \
 185                                | OR_FCM_CST \
 186                                | OR_FCM_CHT \
 187                                | OR_FCM_SCY_1 \
 188                                | OR_FCM_TRLX \
 189                                | OR_FCM_EHTR)
 190
 191 #ifdef CONFIG_MTD_RAW_NAND
 192 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 193 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 194 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 195 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 196 #else
 197 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 198 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 199 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 200 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 201 #endif
 202 #else
 203 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 204 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 205 #endif /* CONFIG_NAND_FSL_ELBC */
 206
 207 #define CONFIG_SYS_FLASH_EMPTY_INFO
 208 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 209 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 210
 211 #define CONFIG_HWCONFIG
 212
 213 /* define to use L1 as initial stack */
 214 #define CONFIG_L1_INIT_RAM
 215 #define CONFIG_SYS_INIT_RAM_LOCK
 216 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 217 #ifdef CONFIG_PHYS_64BIT
 218 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 219 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 220 /* The assembler doesn't like typecast */
 221 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 222         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 223           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 224 #else
 225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 226 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 227 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 228 #endif
 229 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 230
 231 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 232 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 233
 234 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 235
 236 /* Serial Port - controlled on board with jumper J8
 237  * open - index 2
 238  * shorted - index 1
 239  */
 240 #define CONFIG_SYS_NS16550_SERIAL
 241 #define CONFIG_SYS_NS16550_REG_SIZE     1
 242 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 243
 244 #define CONFIG_SYS_BAUDRATE_TABLE       \
 245         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 246
 247 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 248 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 249 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 250 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 251
 252 /* I2C */
 253
 254 /*
 255  * RapidIO
 256  */
 257 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 258 #ifdef CONFIG_PHYS_64BIT
 259 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 260 #else
 261 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 262 #endif
 263 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 264
 265 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 266 #ifdef CONFIG_PHYS_64BIT
 267 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 268 #else
 269 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 270 #endif
 271 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 272
 273 /*
 274  * for slave u-boot IMAGE instored in master memory space,
 275  * PHYS must be aligned based on the SIZE
 276  */
 277 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 278 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 279 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 280 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 281 /*
 282  * for slave UCODE and ENV instored in master memory space,
 283  * PHYS must be aligned based on the SIZE
 284  */
 285 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 286 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 287 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 288
 289 /* slave core release by master*/
 290 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 291 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 292
 293 /*
 294  * SRIO_PCIE_BOOT - SLAVE
 295  */
 296 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 297 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 298 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 299                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 300 #endif
 301
 302 /*
 303  * eSPI - Enhanced SPI
 304  */
 305
 306 /*
 307  * General PCI
 308  * Memory space is mapped 1-1, but I/O space must start from 0.
 309  */
 310
 311 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 312 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 313 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 314 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 315 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 316
 317 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 318 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 319 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 320 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 321 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 322
 323 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 324 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 325 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 326 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 327 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 328
 329 /* controller 4, Base address 203000 */
 330 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 331 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 332
 333 /* Qman/Bman */
 334 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 335 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 336 #ifdef CONFIG_PHYS_64BIT
 337 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 338 #else
 339 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 340 #endif
 341 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 342 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 343 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 344 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 345 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 346 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 347                                         CONFIG_SYS_BMAN_CENA_SIZE)
 348 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 349 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 350 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 351 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 352 #ifdef CONFIG_PHYS_64BIT
 353 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 354 #else
 355 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 356 #endif
 357 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 358 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 359 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 360 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 361 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 362 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 363                                         CONFIG_SYS_QMAN_CENA_SIZE)
 364 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 365 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 366
 367 #define CONFIG_SYS_DPAA_FMAN
 368 #define CONFIG_SYS_DPAA_PME
 369 /* Default address of microcode for the Linux Fman driver */
 370 #if defined(CONFIG_SPIFLASH)
 371 /*
 372  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 373  * env, so we got 0x110000.
 374  */
 375 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 376 #elif defined(CONFIG_SDCARD)
 377 /*
 378  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 379  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 380  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 381  */
 382 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 383 #elif defined(CONFIG_MTD_RAW_NAND)
 384 #define CONFIG_SYS_FMAN_FW_ADDR (8 * (128 * 1024))
 385 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 386 /*
 387  * Slave has no ucode locally, it can fetch this from remote. When implementing
 388  * in two corenet boards, slave's ucode could be stored in master's memory
 389  * space, the address can be mapped from slave TLB->slave LAW->
 390  * slave SRIO or PCIE outbound window->master inbound window->
 391  * master LAW->the ucode address in master's memory space.
 392  */
 393 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 394 #else
 395 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 396 #endif
 397 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 398 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 399
 400 #ifdef CONFIG_PCI
 401 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 402 #endif  /* CONFIG_PCI */
 403
 404 /* SATA */
 405 #ifdef CONFIG_FSL_SATA_V2
 406 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 407 #define CONFIG_SATA1
 408 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 409 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 410 #define CONFIG_SATA2
 411 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 412 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 413
 414 #define CONFIG_LBA48
 415 #endif
 416
 417 #ifdef CONFIG_FMAN_ENET
 418 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 419 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 420 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 421 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 422 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 423
 424 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 425 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 426 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 427 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 428 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 429
 430 #define CONFIG_SYS_TBIPA_VALUE  8
 431 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 432 #endif
 433
 434 /*
 435  * Environment
 436  */
 437 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 438 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 439
 440 /*
 441 * USB
 442 */
 443 #define CONFIG_HAS_FSL_DR_USB
 444 #define CONFIG_HAS_FSL_MPH_USB
 445
 446 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 447 #define CONFIG_USB_EHCI_FSL
 448 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 449 #endif
 450
 451 #ifdef CONFIG_MMC
 452 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 453 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 454 #endif
 455
 456 /*
 457  * Miscellaneous configurable options
 458  */
 459
 460 /*
 461  * For booting Linux, the board info and command line data
 462  * have to be in the first 64 MB of memory, since this is
 463  * the maximum mapped by the Linux kernel during initialization.
 464  */
 465 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 466 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 467
 468 /*
 469  * Environment Configuration
 470  */
 471 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 472 #define CONFIG_BOOTFILE         "uImage"
 473 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 474
 475 #ifdef CONFIG_TARGET_P4080DS
 476 #define __USB_PHY_TYPE  ulpi
 477 #else
 478 #define __USB_PHY_TYPE  utmi
 479 #endif
 480
 481 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 482         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 483         "bank_intlv=cs0_cs1;"                                   \
 484         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 485         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 486         "netdev=eth0\0"                                         \
 487         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 488         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 489         "tftpflash=tftpboot $loadaddr $uboot && "               \
 490         "protect off $ubootaddr +$filesize && "                 \
 491         "erase $ubootaddr +$filesize && "                       \
 492         "cp.b $loadaddr $ubootaddr $filesize && "               \
 493         "protect on $ubootaddr +$filesize && "                  \
 494         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 495         "consoledev=ttyS0\0"                                    \
 496         "ramdiskaddr=2000000\0"                                 \
 497         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 498         "fdtaddr=1e00000\0"                                     \
 499         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 500         "bdev=sda3\0"
 501
 502 #define HDBOOT                                  \
 503         "setenv bootargs root=/dev/$bdev rw "           \
 504         "console=$consoledev,$baudrate $othbootargs;"   \
 505         "tftp $loadaddr $bootfile;"                     \
 506         "tftp $fdtaddr $fdtfile;"                       \
 507         "bootm $loadaddr - $fdtaddr"
 508
 509 #define NFSBOOTCOMMAND                  \
 510         "setenv bootargs root=/dev/nfs rw "     \
 511         "nfsroot=$serverip:$rootpath "          \
 512         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 513         "console=$consoledev,$baudrate $othbootargs;"   \
 514         "tftp $loadaddr $bootfile;"             \
 515         "tftp $fdtaddr $fdtfile;"               \
 516         "bootm $loadaddr - $fdtaddr"
 517
 518 #define RAMBOOTCOMMAND                          \
 519         "setenv bootargs root=/dev/ram rw "             \
 520         "console=$consoledev,$baudrate $othbootargs;"   \
 521         "tftp $ramdiskaddr $ramdiskfile;"               \
 522         "tftp $loadaddr $bootfile;"                     \
 523         "tftp $fdtaddr $fdtfile;"                       \
 524         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 525
 526 #define CONFIG_BOOTCOMMAND              HDBOOT
 527
 528 #include <asm/fsl_secure_boot.h>
 529
 530 #endif  /* __CONFIG_H */