2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * Corenet DS style board configuration file
13 #include "../board/freescale/common/ics307_clk.h"
15 #ifdef CONFIG_RAMBOOT_PBL
16 #ifdef CONFIG_SECURE_BOOT
17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
20 #define CONFIG_RAMBOOT_NAND
22 #define CONFIG_BOOTSCRIPT_COPY_RAM
24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
27 #if defined(CONFIG_TARGET_P3041DS)
28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
29 #elif defined(CONFIG_TARGET_P4080DS)
30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
31 #elif defined(CONFIG_TARGET_P5020DS)
32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
33 #elif defined(CONFIG_TARGET_P5040DS)
34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
40 /* Set 1M boot space */
41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
47 /* High Level Configuration Options */
48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
49 #define CONFIG_MP /* support multiple processors */
51 #ifndef CONFIG_RESET_VECTOR_ADDRESS
52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
56 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
57 #define CONFIG_PCIE1 /* PCIE controller 1 */
58 #define CONFIG_PCIE2 /* PCIE controller 2 */
59 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
62 #define CONFIG_ENV_OVERWRITE
64 #ifndef CONFIG_MTD_NOR_FLASH
66 #define CONFIG_FLASH_CFI_DRIVER
67 #define CONFIG_SYS_FLASH_CFI
68 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
71 #if defined(CONFIG_SPIFLASH)
72 #define CONFIG_SYS_EXTRA_ENV_RELOC
73 #define CONFIG_ENV_SPI_BUS 0
74 #define CONFIG_ENV_SPI_CS 0
75 #define CONFIG_ENV_SPI_MAX_HZ 10000000
76 #define CONFIG_ENV_SPI_MODE 0
77 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
78 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
79 #define CONFIG_ENV_SECT_SIZE 0x10000
80 #elif defined(CONFIG_SDCARD)
81 #define CONFIG_SYS_EXTRA_ENV_RELOC
82 #define CONFIG_FSL_FIXED_MMC_LOCATION
83 #define CONFIG_SYS_MMC_ENV_DEV 0
84 #define CONFIG_ENV_SIZE 0x2000
85 #define CONFIG_ENV_OFFSET (512 * 1658)
86 #elif defined(CONFIG_NAND)
87 #define CONFIG_SYS_EXTRA_ENV_RELOC
88 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
89 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
90 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
91 #define CONFIG_ENV_ADDR 0xffe20000
92 #define CONFIG_ENV_SIZE 0x2000
93 #elif defined(CONFIG_ENV_IS_NOWHERE)
94 #define CONFIG_ENV_SIZE 0x2000
96 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
97 #define CONFIG_ENV_SIZE 0x2000
98 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
101 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
104 * These can be toggled for performance analysis, otherwise use default.
106 #define CONFIG_SYS_CACHE_STASHING
107 #define CONFIG_BACKSIDE_L2_CACHE
108 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
109 #define CONFIG_BTB /* toggle branch predition */
110 #define CONFIG_DDR_ECC
111 #ifdef CONFIG_DDR_ECC
112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
113 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
116 #define CONFIG_ENABLE_36BIT_PHYS
118 #ifdef CONFIG_PHYS_64BIT
119 #define CONFIG_ADDR_MAP
120 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
123 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
124 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
125 #define CONFIG_SYS_MEMTEST_END 0x00400000
126 #define CONFIG_SYS_ALT_MEMTEST
129 * Config the L3 Cache as L3 SRAM
131 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
132 #ifdef CONFIG_PHYS_64BIT
133 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
135 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
137 #define CONFIG_SYS_L3_SIZE (1024 << 10)
138 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
140 #ifdef CONFIG_PHYS_64BIT
141 #define CONFIG_SYS_DCSRBAR 0xf0000000
142 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
146 #define CONFIG_ID_EEPROM
147 #define CONFIG_SYS_I2C_EEPROM_NXID
148 #define CONFIG_SYS_EEPROM_BUS_NUM 0
149 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
150 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
155 #define CONFIG_VERY_BIG_RAM
156 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
157 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
159 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
160 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
162 #define CONFIG_DDR_SPD
164 #define CONFIG_SYS_SPD_BUS_NUM 1
165 #define SPD_EEPROM_ADDRESS1 0x51
166 #define SPD_EEPROM_ADDRESS2 0x52
167 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
168 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
171 * Local Bus Definitions
174 /* Set the local bus clock 1/8 of platform clock */
175 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
177 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
178 #ifdef CONFIG_PHYS_64BIT
179 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
181 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
184 #define CONFIG_SYS_FLASH_BR_PRELIM \
185 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
187 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
188 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
190 #define CONFIG_SYS_BR1_PRELIM \
191 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
192 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
194 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
195 #ifdef CONFIG_PHYS_64BIT
196 #define PIXIS_BASE_PHYS 0xfffdf0000ull
198 #define PIXIS_BASE_PHYS PIXIS_BASE
201 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
202 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
204 #define PIXIS_LBMAP_SWITCH 7
205 #define PIXIS_LBMAP_MASK 0xf0
206 #define PIXIS_LBMAP_SHIFT 4
207 #define PIXIS_LBMAP_ALTBANK 0x40
209 #define CONFIG_SYS_FLASH_QUIET_TEST
210 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
212 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
213 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
214 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
215 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
217 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
219 #if defined(CONFIG_RAMBOOT_PBL)
220 #define CONFIG_SYS_RAMBOOT
224 #ifdef CONFIG_NAND_FSL_ELBC
225 #define CONFIG_SYS_NAND_BASE 0xffa00000
226 #ifdef CONFIG_PHYS_64BIT
227 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
229 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
232 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
233 #define CONFIG_SYS_MAX_NAND_DEVICE 1
234 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
236 /* NAND flash config */
237 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
238 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
239 | BR_PS_8 /* Port Size = 8 bit */ \
240 | BR_MS_FCM /* MSEL = FCM */ \
242 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
243 | OR_FCM_PGS /* Large Page*/ \
252 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
253 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
254 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
255 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
257 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
258 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
259 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
260 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
263 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
264 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
265 #endif /* CONFIG_NAND_FSL_ELBC */
267 #define CONFIG_SYS_FLASH_EMPTY_INFO
268 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
269 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
271 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
272 #define CONFIG_MISC_INIT_R
274 #define CONFIG_HWCONFIG
276 /* define to use L1 as initial stack */
277 #define CONFIG_L1_INIT_RAM
278 #define CONFIG_SYS_INIT_RAM_LOCK
279 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
280 #ifdef CONFIG_PHYS_64BIT
281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
282 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
283 /* The assembler doesn't like typecast */
284 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
285 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
286 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
292 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
294 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
295 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
297 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
298 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
300 /* Serial Port - controlled on board with jumper J8
304 #define CONFIG_SYS_NS16550_SERIAL
305 #define CONFIG_SYS_NS16550_REG_SIZE 1
306 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
308 #define CONFIG_SYS_BAUDRATE_TABLE \
309 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
311 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
312 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
313 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
314 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
317 #define CONFIG_SYS_I2C
318 #define CONFIG_SYS_I2C_FSL
319 #define CONFIG_SYS_FSL_I2C_SPEED 400000
320 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
321 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
322 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
323 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
324 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
329 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
330 #ifdef CONFIG_PHYS_64BIT
331 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
333 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
335 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
337 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
338 #ifdef CONFIG_PHYS_64BIT
339 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
341 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
343 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
346 * for slave u-boot IMAGE instored in master memory space,
347 * PHYS must be aligned based on the SIZE
349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
354 * for slave UCODE and ENV instored in master memory space,
355 * PHYS must be aligned based on the SIZE
357 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
361 /* slave core release by master*/
362 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
363 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
366 * SRIO_PCIE_BOOT - SLAVE
368 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
369 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
370 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
371 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
375 * eSPI - Enhanced SPI
377 #define CONFIG_SF_DEFAULT_SPEED 10000000
378 #define CONFIG_SF_DEFAULT_MODE 0
382 * Memory space is mapped 1-1, but I/O space must start from 0.
385 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
386 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
387 #ifdef CONFIG_PHYS_64BIT
388 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
389 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
391 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
392 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
394 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
395 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
396 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
397 #ifdef CONFIG_PHYS_64BIT
398 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
400 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
402 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
404 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
405 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
406 #ifdef CONFIG_PHYS_64BIT
407 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
408 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
410 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
411 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
413 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
414 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
415 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
416 #ifdef CONFIG_PHYS_64BIT
417 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
419 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
421 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
423 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
424 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
425 #ifdef CONFIG_PHYS_64BIT
426 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
427 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
429 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
430 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
432 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
433 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
434 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
435 #ifdef CONFIG_PHYS_64BIT
436 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
438 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
440 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
442 /* controller 4, Base address 203000 */
443 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
444 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
445 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
446 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
447 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
448 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
451 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
452 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
453 #ifdef CONFIG_PHYS_64BIT
454 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
456 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
458 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
459 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
460 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
461 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
462 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
463 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
464 CONFIG_SYS_BMAN_CENA_SIZE)
465 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
466 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
467 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
468 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
469 #ifdef CONFIG_PHYS_64BIT
470 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
472 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
474 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
475 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
476 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
477 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
478 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
479 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
480 CONFIG_SYS_QMAN_CENA_SIZE)
481 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
482 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
484 #define CONFIG_SYS_DPAA_FMAN
485 #define CONFIG_SYS_DPAA_PME
486 /* Default address of microcode for the Linux Fman driver */
487 #if defined(CONFIG_SPIFLASH)
489 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
490 * env, so we got 0x110000.
492 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
493 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
494 #elif defined(CONFIG_SDCARD)
496 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
497 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
498 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
500 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
501 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
502 #elif defined(CONFIG_NAND)
503 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
504 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
505 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
507 * Slave has no ucode locally, it can fetch this from remote. When implementing
508 * in two corenet boards, slave's ucode could be stored in master's memory
509 * space, the address can be mapped from slave TLB->slave LAW->
510 * slave SRIO or PCIE outbound window->master inbound window->
511 * master LAW->the ucode address in master's memory space.
513 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
514 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
516 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
517 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
519 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
520 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
522 #ifdef CONFIG_SYS_DPAA_FMAN
523 #define CONFIG_FMAN_ENET
524 #define CONFIG_PHYLIB_10G
525 #define CONFIG_PHY_VITESSE
526 #define CONFIG_PHY_TERANETICS
530 #define CONFIG_PCI_INDIRECT_BRIDGE
532 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
533 #endif /* CONFIG_PCI */
536 #ifdef CONFIG_FSL_SATA_V2
537 #define CONFIG_SYS_SATA_MAX_DEVICE 2
539 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
540 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
542 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
543 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
548 #ifdef CONFIG_FMAN_ENET
549 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
550 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
551 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
552 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
553 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
555 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
556 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
557 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
558 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
559 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
561 #define CONFIG_SYS_TBIPA_VALUE 8
562 #define CONFIG_MII /* MII PHY management */
563 #define CONFIG_ETHPRIME "FM1@DTSEC1"
569 #define CONFIG_LOADS_ECHO /* echo on for serial download */
570 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
575 #define CONFIG_HAS_FSL_DR_USB
576 #define CONFIG_HAS_FSL_MPH_USB
578 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
579 #define CONFIG_USB_EHCI_FSL
580 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
584 #define CONFIG_FSL_ESDHC
585 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
586 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
590 * Miscellaneous configurable options
592 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
595 * For booting Linux, the board info and command line data
596 * have to be in the first 64 MB of memory, since this is
597 * the maximum mapped by the Linux kernel during initialization.
599 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
600 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
602 #ifdef CONFIG_CMD_KGDB
603 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
607 * Environment Configuration
609 #define CONFIG_ROOTPATH "/opt/nfsroot"
610 #define CONFIG_BOOTFILE "uImage"
611 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
613 /* default location for tftp and bootm */
614 #define CONFIG_LOADADDR 1000000
616 #ifdef CONFIG_TARGET_P4080DS
617 #define __USB_PHY_TYPE ulpi
619 #define __USB_PHY_TYPE utmi
622 #define CONFIG_EXTRA_ENV_SETTINGS \
623 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
624 "bank_intlv=cs0_cs1;" \
625 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
626 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
628 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
629 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
630 "tftpflash=tftpboot $loadaddr $uboot && " \
631 "protect off $ubootaddr +$filesize && " \
632 "erase $ubootaddr +$filesize && " \
633 "cp.b $loadaddr $ubootaddr $filesize && " \
634 "protect on $ubootaddr +$filesize && " \
635 "cmp.b $loadaddr $ubootaddr $filesize\0" \
636 "consoledev=ttyS0\0" \
637 "ramdiskaddr=2000000\0" \
638 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
639 "fdtaddr=1e00000\0" \
640 "fdtfile=p4080ds/p4080ds.dtb\0" \
643 #define CONFIG_HDBOOT \
644 "setenv bootargs root=/dev/$bdev rw " \
645 "console=$consoledev,$baudrate $othbootargs;" \
646 "tftp $loadaddr $bootfile;" \
647 "tftp $fdtaddr $fdtfile;" \
648 "bootm $loadaddr - $fdtaddr"
650 #define CONFIG_NFSBOOTCOMMAND \
651 "setenv bootargs root=/dev/nfs rw " \
652 "nfsroot=$serverip:$rootpath " \
653 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
654 "console=$consoledev,$baudrate $othbootargs;" \
655 "tftp $loadaddr $bootfile;" \
656 "tftp $fdtaddr $fdtfile;" \
657 "bootm $loadaddr - $fdtaddr"
659 #define CONFIG_RAMBOOTCOMMAND \
660 "setenv bootargs root=/dev/ram rw " \
661 "console=$consoledev,$baudrate $othbootargs;" \
662 "tftp $ramdiskaddr $ramdiskfile;" \
663 "tftp $loadaddr $bootfile;" \
664 "tftp $fdtaddr $fdtfile;" \
665 "bootm $loadaddr $ramdiskaddr $fdtaddr"
667 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
669 #include <asm/fsl_secure_boot.h>
671 #endif /* __CONFIG_H */