1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
8 * Corenet DS style board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
17 #ifdef CONFIG_RAMBOOT_PBL
18 #ifdef CONFIG_NXP_ESBC
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21 #ifdef CONFIG_MTD_RAW_NAND
22 #define CONFIG_RAMBOOT_NAND
24 #define CONFIG_BOOTSCRIPT_COPY_RAM
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
29 #if defined(CONFIG_TARGET_P3041DS)
30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
31 #elif defined(CONFIG_TARGET_P4080DS)
32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
33 #elif defined(CONFIG_TARGET_P5020DS)
34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
35 #elif defined(CONFIG_TARGET_P5040DS)
36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
42 /* Set 1M boot space */
43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
45 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
49 /* High Level Configuration Options */
50 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
57 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
58 #define CONFIG_PCIE1 /* PCIE controller 1 */
59 #define CONFIG_PCIE2 /* PCIE controller 2 */
60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
62 #define CONFIG_ENV_OVERWRITE
64 #if defined(CONFIG_SPIFLASH)
65 #elif defined(CONFIG_SDCARD)
66 #define CONFIG_FSL_FIXED_MMC_LOCATION
67 #define CONFIG_SYS_MMC_ENV_DEV 0
70 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
73 * These can be toggled for performance analysis, otherwise use default.
75 #define CONFIG_SYS_CACHE_STASHING
76 #define CONFIG_BACKSIDE_L2_CACHE
77 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
78 #define CONFIG_BTB /* toggle branch predition */
79 #define CONFIG_DDR_ECC
81 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
82 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
85 #define CONFIG_ENABLE_36BIT_PHYS
87 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
90 * Config the L3 Cache as L3 SRAM
92 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
93 #ifdef CONFIG_PHYS_64BIT
94 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
96 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
98 #define CONFIG_SYS_L3_SIZE (1024 << 10)
99 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
101 #ifdef CONFIG_PHYS_64BIT
102 #define CONFIG_SYS_DCSRBAR 0xf0000000
103 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
107 #define CONFIG_ID_EEPROM
108 #define CONFIG_SYS_I2C_EEPROM_NXID
109 #define CONFIG_SYS_EEPROM_BUS_NUM 0
110 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
111 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
116 #define CONFIG_VERY_BIG_RAM
117 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
118 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
120 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
121 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
123 #define CONFIG_DDR_SPD
125 #define CONFIG_SYS_SPD_BUS_NUM 1
126 #define SPD_EEPROM_ADDRESS1 0x51
127 #define SPD_EEPROM_ADDRESS2 0x52
128 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
129 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
132 * Local Bus Definitions
135 /* Set the local bus clock 1/8 of platform clock */
136 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
138 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
139 #ifdef CONFIG_PHYS_64BIT
140 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
142 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
145 #define CONFIG_SYS_FLASH_BR_PRELIM \
146 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
148 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
149 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
151 #define CONFIG_SYS_BR1_PRELIM \
152 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
153 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
155 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
156 #ifdef CONFIG_PHYS_64BIT
157 #define PIXIS_BASE_PHYS 0xfffdf0000ull
159 #define PIXIS_BASE_PHYS PIXIS_BASE
162 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
163 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
165 #define PIXIS_LBMAP_SWITCH 7
166 #define PIXIS_LBMAP_MASK 0xf0
167 #define PIXIS_LBMAP_SHIFT 4
168 #define PIXIS_LBMAP_ALTBANK 0x40
170 #define CONFIG_SYS_FLASH_QUIET_TEST
171 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
173 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
174 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
175 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
176 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
178 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
180 #if defined(CONFIG_RAMBOOT_PBL)
181 #define CONFIG_SYS_RAMBOOT
185 #ifdef CONFIG_NAND_FSL_ELBC
186 #define CONFIG_SYS_NAND_BASE 0xffa00000
187 #ifdef CONFIG_PHYS_64BIT
188 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
190 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
193 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
194 #define CONFIG_SYS_MAX_NAND_DEVICE 1
195 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
197 /* NAND flash config */
198 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
199 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
200 | BR_PS_8 /* Port Size = 8 bit */ \
201 | BR_MS_FCM /* MSEL = FCM */ \
203 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
204 | OR_FCM_PGS /* Large Page*/ \
212 #ifdef CONFIG_MTD_RAW_NAND
213 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
214 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
215 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
216 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
218 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
219 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
220 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
221 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
224 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
225 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
226 #endif /* CONFIG_NAND_FSL_ELBC */
228 #define CONFIG_SYS_FLASH_EMPTY_INFO
229 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
230 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
232 #define CONFIG_HWCONFIG
234 /* define to use L1 as initial stack */
235 #define CONFIG_L1_INIT_RAM
236 #define CONFIG_SYS_INIT_RAM_LOCK
237 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
238 #ifdef CONFIG_PHYS_64BIT
239 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
240 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
241 /* The assembler doesn't like typecast */
242 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
243 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
244 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
246 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
247 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
248 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
250 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
252 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
253 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
255 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
256 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
258 /* Serial Port - controlled on board with jumper J8
262 #define CONFIG_SYS_NS16550_SERIAL
263 #define CONFIG_SYS_NS16550_REG_SIZE 1
264 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
266 #define CONFIG_SYS_BAUDRATE_TABLE \
267 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
269 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
270 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
271 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
272 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
275 #ifndef CONFIG_DM_I2C
276 #define CONFIG_SYS_I2C
277 #define CONFIG_SYS_FSL_I2C_SPEED 400000
278 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
279 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
280 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
281 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
282 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
284 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
285 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
287 #define CONFIG_SYS_I2C_FSL
292 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
293 #ifdef CONFIG_PHYS_64BIT
294 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
296 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
298 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
300 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
301 #ifdef CONFIG_PHYS_64BIT
302 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
304 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
306 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
309 * for slave u-boot IMAGE instored in master memory space,
310 * PHYS must be aligned based on the SIZE
312 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
313 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
314 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
315 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
317 * for slave UCODE and ENV instored in master memory space,
318 * PHYS must be aligned based on the SIZE
320 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
321 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
322 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
324 /* slave core release by master*/
325 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
326 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
329 * SRIO_PCIE_BOOT - SLAVE
331 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
332 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
333 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
334 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
338 * eSPI - Enhanced SPI
343 * Memory space is mapped 1-1, but I/O space must start from 0.
346 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
347 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
348 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
349 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
350 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
352 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
353 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
354 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
355 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
356 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
358 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
359 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
360 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
361 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
362 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
364 /* controller 4, Base address 203000 */
365 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
366 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
369 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
370 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
371 #ifdef CONFIG_PHYS_64BIT
372 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
374 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
376 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
377 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
378 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
379 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
380 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
381 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
382 CONFIG_SYS_BMAN_CENA_SIZE)
383 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
384 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
385 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
386 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
387 #ifdef CONFIG_PHYS_64BIT
388 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
390 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
392 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
393 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
394 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
395 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
396 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
397 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
398 CONFIG_SYS_QMAN_CENA_SIZE)
399 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
400 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
402 #define CONFIG_SYS_DPAA_FMAN
403 #define CONFIG_SYS_DPAA_PME
404 /* Default address of microcode for the Linux Fman driver */
405 #if defined(CONFIG_SPIFLASH)
407 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
408 * env, so we got 0x110000.
410 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
411 #elif defined(CONFIG_SDCARD)
413 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
414 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
415 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
417 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
418 #elif defined(CONFIG_MTD_RAW_NAND)
419 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
420 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
422 * Slave has no ucode locally, it can fetch this from remote. When implementing
423 * in two corenet boards, slave's ucode could be stored in master's memory
424 * space, the address can be mapped from slave TLB->slave LAW->
425 * slave SRIO or PCIE outbound window->master inbound window->
426 * master LAW->the ucode address in master's memory space.
428 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
430 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
432 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
433 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
436 #if !defined(CONFIG_DM_PCI)
437 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
438 #define CONFIG_PCI_INDIRECT_BRIDGE
439 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
440 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
441 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
442 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
443 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
444 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
445 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
446 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
447 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
448 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
449 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
450 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
451 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
452 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
453 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
454 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
457 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
458 #endif /* CONFIG_PCI */
461 #ifdef CONFIG_FSL_SATA_V2
462 #define CONFIG_SYS_SATA_MAX_DEVICE 2
464 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
465 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
467 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
468 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
473 #ifdef CONFIG_FMAN_ENET
474 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
475 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
476 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
477 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
478 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
480 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
481 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
482 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
483 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
484 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
486 #define CONFIG_SYS_TBIPA_VALUE 8
487 #define CONFIG_ETHPRIME "FM1@DTSEC1"
493 #define CONFIG_LOADS_ECHO /* echo on for serial download */
494 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
499 #define CONFIG_HAS_FSL_DR_USB
500 #define CONFIG_HAS_FSL_MPH_USB
502 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
503 #define CONFIG_USB_EHCI_FSL
504 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
508 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
509 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
513 * Miscellaneous configurable options
515 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
518 * For booting Linux, the board info and command line data
519 * have to be in the first 64 MB of memory, since this is
520 * the maximum mapped by the Linux kernel during initialization.
522 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
523 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
525 #ifdef CONFIG_CMD_KGDB
526 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
530 * Environment Configuration
532 #define CONFIG_ROOTPATH "/opt/nfsroot"
533 #define CONFIG_BOOTFILE "uImage"
534 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
536 /* default location for tftp and bootm */
537 #define CONFIG_LOADADDR 1000000
539 #ifdef CONFIG_TARGET_P4080DS
540 #define __USB_PHY_TYPE ulpi
542 #define __USB_PHY_TYPE utmi
545 #define CONFIG_EXTRA_ENV_SETTINGS \
546 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
547 "bank_intlv=cs0_cs1;" \
548 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
549 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
551 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
552 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
553 "tftpflash=tftpboot $loadaddr $uboot && " \
554 "protect off $ubootaddr +$filesize && " \
555 "erase $ubootaddr +$filesize && " \
556 "cp.b $loadaddr $ubootaddr $filesize && " \
557 "protect on $ubootaddr +$filesize && " \
558 "cmp.b $loadaddr $ubootaddr $filesize\0" \
559 "consoledev=ttyS0\0" \
560 "ramdiskaddr=2000000\0" \
561 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
562 "fdtaddr=1e00000\0" \
563 "fdtfile=p4080ds/p4080ds.dtb\0" \
566 #define CONFIG_HDBOOT \
567 "setenv bootargs root=/dev/$bdev rw " \
568 "console=$consoledev,$baudrate $othbootargs;" \
569 "tftp $loadaddr $bootfile;" \
570 "tftp $fdtaddr $fdtfile;" \
571 "bootm $loadaddr - $fdtaddr"
573 #define CONFIG_NFSBOOTCOMMAND \
574 "setenv bootargs root=/dev/nfs rw " \
575 "nfsroot=$serverip:$rootpath " \
576 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
577 "console=$consoledev,$baudrate $othbootargs;" \
578 "tftp $loadaddr $bootfile;" \
579 "tftp $fdtaddr $fdtfile;" \
580 "bootm $loadaddr - $fdtaddr"
582 #define CONFIG_RAMBOOTCOMMAND \
583 "setenv bootargs root=/dev/ram rw " \
584 "console=$consoledev,$baudrate $othbootargs;" \
585 "tftp $ramdiskaddr $ramdiskfile;" \
586 "tftp $loadaddr $bootfile;" \
587 "tftp $fdtaddr $fdtfile;" \
588 "bootm $loadaddr $ramdiskaddr $fdtaddr"
590 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
592 #include <asm/fsl_secure_boot.h>
594 #endif /* __CONFIG_H */