1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
8 * Corenet DS style board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
17 #ifdef CONFIG_RAMBOOT_PBL
18 #ifdef CONFIG_NXP_ESBC
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21 #ifdef CONFIG_MTD_RAW_NAND
22 #define CONFIG_RAMBOOT_NAND
24 #define CONFIG_BOOTSCRIPT_COPY_RAM
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
28 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
29 #if defined(CONFIG_TARGET_P3041DS)
30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
31 #elif defined(CONFIG_TARGET_P4080DS)
32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
33 #elif defined(CONFIG_TARGET_P5020DS)
34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
35 #elif defined(CONFIG_TARGET_P5040DS)
36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
42 /* Set 1M boot space */
43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
45 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
49 /* High Level Configuration Options */
50 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
57 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
58 #define CONFIG_PCIE1 /* PCIE controller 1 */
59 #define CONFIG_PCIE2 /* PCIE controller 2 */
60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
62 #if defined(CONFIG_SPIFLASH)
63 #elif defined(CONFIG_SDCARD)
64 #define CONFIG_FSL_FIXED_MMC_LOCATION
67 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
70 * These can be toggled for performance analysis, otherwise use default.
72 #define CONFIG_SYS_CACHE_STASHING
73 #define CONFIG_BACKSIDE_L2_CACHE
74 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
75 #define CONFIG_BTB /* toggle branch predition */
77 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
80 #define CONFIG_ENABLE_36BIT_PHYS
82 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
85 * Config the L3 Cache as L3 SRAM
87 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
88 #ifdef CONFIG_PHYS_64BIT
89 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
91 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
93 #define CONFIG_SYS_L3_SIZE (1024 << 10)
94 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
96 #ifdef CONFIG_PHYS_64BIT
97 #define CONFIG_SYS_DCSRBAR 0xf0000000
98 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
102 #define CONFIG_SYS_I2C_EEPROM_NXID
103 #define CONFIG_SYS_EEPROM_BUS_NUM 0
108 #define CONFIG_VERY_BIG_RAM
109 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
110 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
112 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
113 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
115 #define CONFIG_SYS_SPD_BUS_NUM 1
116 #define SPD_EEPROM_ADDRESS1 0x51
117 #define SPD_EEPROM_ADDRESS2 0x52
118 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
119 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
122 * Local Bus Definitions
125 /* Set the local bus clock 1/8 of platform clock */
126 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
128 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
129 #ifdef CONFIG_PHYS_64BIT
130 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
132 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
135 #define CONFIG_SYS_FLASH_BR_PRELIM \
136 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
138 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
139 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
141 #define CONFIG_SYS_BR1_PRELIM \
142 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
143 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
145 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
146 #ifdef CONFIG_PHYS_64BIT
147 #define PIXIS_BASE_PHYS 0xfffdf0000ull
149 #define PIXIS_BASE_PHYS PIXIS_BASE
152 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
153 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
155 #define PIXIS_LBMAP_SWITCH 7
156 #define PIXIS_LBMAP_MASK 0xf0
157 #define PIXIS_LBMAP_SHIFT 4
158 #define PIXIS_LBMAP_ALTBANK 0x40
160 #define CONFIG_SYS_FLASH_QUIET_TEST
161 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
163 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
164 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
165 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
166 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
168 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
170 #if defined(CONFIG_RAMBOOT_PBL)
171 #define CONFIG_SYS_RAMBOOT
175 #ifdef CONFIG_NAND_FSL_ELBC
176 #define CONFIG_SYS_NAND_BASE 0xffa00000
177 #ifdef CONFIG_PHYS_64BIT
178 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
180 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
183 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
184 #define CONFIG_SYS_MAX_NAND_DEVICE 1
185 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
187 /* NAND flash config */
188 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
189 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
190 | BR_PS_8 /* Port Size = 8 bit */ \
191 | BR_MS_FCM /* MSEL = FCM */ \
193 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
194 | OR_FCM_PGS /* Large Page*/ \
202 #ifdef CONFIG_MTD_RAW_NAND
203 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
204 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
205 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
206 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
208 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
209 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
210 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
211 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
214 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
215 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
216 #endif /* CONFIG_NAND_FSL_ELBC */
218 #define CONFIG_SYS_FLASH_EMPTY_INFO
219 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
220 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
222 #define CONFIG_HWCONFIG
224 /* define to use L1 as initial stack */
225 #define CONFIG_L1_INIT_RAM
226 #define CONFIG_SYS_INIT_RAM_LOCK
227 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
228 #ifdef CONFIG_PHYS_64BIT
229 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
230 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
231 /* The assembler doesn't like typecast */
232 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
233 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
234 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
236 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
237 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
238 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
240 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
242 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
243 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
245 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
246 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
248 /* Serial Port - controlled on board with jumper J8
252 #define CONFIG_SYS_NS16550_SERIAL
253 #define CONFIG_SYS_NS16550_REG_SIZE 1
254 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
256 #define CONFIG_SYS_BAUDRATE_TABLE \
257 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
259 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
260 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
261 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
262 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
269 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
270 #ifdef CONFIG_PHYS_64BIT
271 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
273 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
275 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
277 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
278 #ifdef CONFIG_PHYS_64BIT
279 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
281 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
283 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
286 * for slave u-boot IMAGE instored in master memory space,
287 * PHYS must be aligned based on the SIZE
289 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
290 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
291 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
292 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
294 * for slave UCODE and ENV instored in master memory space,
295 * PHYS must be aligned based on the SIZE
297 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
298 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
299 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
301 /* slave core release by master*/
302 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
303 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
306 * SRIO_PCIE_BOOT - SLAVE
308 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
309 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
310 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
311 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
315 * eSPI - Enhanced SPI
320 * Memory space is mapped 1-1, but I/O space must start from 0.
323 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
324 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
325 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
326 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
327 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
329 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
330 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
331 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
332 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
333 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
335 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
336 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
337 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
338 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
339 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
341 /* controller 4, Base address 203000 */
342 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
343 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
346 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
347 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
348 #ifdef CONFIG_PHYS_64BIT
349 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
351 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
353 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
354 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
355 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
356 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
357 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
358 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
359 CONFIG_SYS_BMAN_CENA_SIZE)
360 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
361 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
362 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
363 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
364 #ifdef CONFIG_PHYS_64BIT
365 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
367 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
369 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
370 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
371 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
372 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
373 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
374 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
375 CONFIG_SYS_QMAN_CENA_SIZE)
376 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
377 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
379 #define CONFIG_SYS_DPAA_FMAN
380 #define CONFIG_SYS_DPAA_PME
381 /* Default address of microcode for the Linux Fman driver */
382 #if defined(CONFIG_SPIFLASH)
384 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
385 * env, so we got 0x110000.
387 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
388 #elif defined(CONFIG_SDCARD)
390 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
391 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
392 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
394 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
395 #elif defined(CONFIG_MTD_RAW_NAND)
396 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
397 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
399 * Slave has no ucode locally, it can fetch this from remote. When implementing
400 * in two corenet boards, slave's ucode could be stored in master's memory
401 * space, the address can be mapped from slave TLB->slave LAW->
402 * slave SRIO or PCIE outbound window->master inbound window->
403 * master LAW->the ucode address in master's memory space.
405 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
407 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
409 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
410 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
413 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
414 #endif /* CONFIG_PCI */
417 #ifdef CONFIG_FSL_SATA_V2
418 #define CONFIG_SYS_SATA_MAX_DEVICE 2
420 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
421 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
423 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
424 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
429 #ifdef CONFIG_FMAN_ENET
430 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
431 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
432 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
433 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
434 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
436 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
437 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
438 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
439 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
440 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
442 #define CONFIG_SYS_TBIPA_VALUE 8
443 #define CONFIG_ETHPRIME "FM1@DTSEC1"
449 #define CONFIG_LOADS_ECHO /* echo on for serial download */
450 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
455 #define CONFIG_HAS_FSL_DR_USB
456 #define CONFIG_HAS_FSL_MPH_USB
458 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
459 #define CONFIG_USB_EHCI_FSL
460 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
464 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
465 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
469 * Miscellaneous configurable options
473 * For booting Linux, the board info and command line data
474 * have to be in the first 64 MB of memory, since this is
475 * the maximum mapped by the Linux kernel during initialization.
477 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
478 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
480 #ifdef CONFIG_CMD_KGDB
481 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
485 * Environment Configuration
487 #define CONFIG_ROOTPATH "/opt/nfsroot"
488 #define CONFIG_BOOTFILE "uImage"
489 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
491 #ifdef CONFIG_TARGET_P4080DS
492 #define __USB_PHY_TYPE ulpi
494 #define __USB_PHY_TYPE utmi
497 #define CONFIG_EXTRA_ENV_SETTINGS \
498 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
499 "bank_intlv=cs0_cs1;" \
500 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
501 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
503 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
504 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
505 "tftpflash=tftpboot $loadaddr $uboot && " \
506 "protect off $ubootaddr +$filesize && " \
507 "erase $ubootaddr +$filesize && " \
508 "cp.b $loadaddr $ubootaddr $filesize && " \
509 "protect on $ubootaddr +$filesize && " \
510 "cmp.b $loadaddr $ubootaddr $filesize\0" \
511 "consoledev=ttyS0\0" \
512 "ramdiskaddr=2000000\0" \
513 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
514 "fdtaddr=1e00000\0" \
515 "fdtfile=p4080ds/p4080ds.dtb\0" \
519 "setenv bootargs root=/dev/$bdev rw " \
520 "console=$consoledev,$baudrate $othbootargs;" \
521 "tftp $loadaddr $bootfile;" \
522 "tftp $fdtaddr $fdtfile;" \
523 "bootm $loadaddr - $fdtaddr"
525 #define NFSBOOTCOMMAND \
526 "setenv bootargs root=/dev/nfs rw " \
527 "nfsroot=$serverip:$rootpath " \
528 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
529 "console=$consoledev,$baudrate $othbootargs;" \
530 "tftp $loadaddr $bootfile;" \
531 "tftp $fdtaddr $fdtfile;" \
532 "bootm $loadaddr - $fdtaddr"
534 #define RAMBOOTCOMMAND \
535 "setenv bootargs root=/dev/ram rw " \
536 "console=$consoledev,$baudrate $othbootargs;" \
537 "tftp $ramdiskaddr $ramdiskfile;" \
538 "tftp $loadaddr $bootfile;" \
539 "tftp $fdtaddr $fdtfile;" \
540 "bootm $loadaddr $ramdiskaddr $fdtaddr"
542 #define CONFIG_BOOTCOMMAND HDBOOT
544 #include <asm/fsl_secure_boot.h>
546 #endif /* __CONFIG_H */