1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * Corenet DS style board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
17 #ifdef CONFIG_RAMBOOT_PBL
18 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
19 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
22 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
23 /* Set 1M boot space */
24 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
25 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
26 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
30 /* High Level Configuration Options */
31 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
33 #ifndef CONFIG_RESET_VECTOR_ADDRESS
34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
37 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
38 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
41 * These can be toggled for performance analysis, otherwise use default.
43 #define CONFIG_SYS_CACHE_STASHING
44 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
49 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
52 * Config the L3 Cache as L3 SRAM
54 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
55 #ifdef CONFIG_PHYS_64BIT
56 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
58 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
60 #define CONFIG_SYS_L3_SIZE (1024 << 10)
61 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
63 #ifdef CONFIG_PHYS_64BIT
64 #define CONFIG_SYS_DCSRBAR 0xf0000000
65 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
69 #define CONFIG_SYS_I2C_EEPROM_NXID
70 #define CONFIG_SYS_EEPROM_BUS_NUM 0
75 #define CONFIG_VERY_BIG_RAM
76 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
79 #define SPD_EEPROM_ADDRESS1 0x51
80 #define SPD_EEPROM_ADDRESS2 0x52
81 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
82 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
85 * Local Bus Definitions
88 /* Set the local bus clock 1/8 of platform clock */
89 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
91 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
92 #ifdef CONFIG_PHYS_64BIT
93 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
95 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
98 #define CONFIG_SYS_FLASH_BR_PRELIM \
99 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
101 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
102 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
104 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
105 #ifdef CONFIG_PHYS_64BIT
106 #define PIXIS_BASE_PHYS 0xfffdf0000ull
108 #define PIXIS_BASE_PHYS PIXIS_BASE
111 #define PIXIS_LBMAP_SWITCH 7
112 #define PIXIS_LBMAP_MASK 0xf0
113 #define PIXIS_LBMAP_SHIFT 4
114 #define PIXIS_LBMAP_ALTBANK 0x40
116 #define CONFIG_SYS_FLASH_QUIET_TEST
117 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
119 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
120 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
121 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
123 #if defined(CONFIG_RAMBOOT_PBL)
124 #define CONFIG_SYS_RAMBOOT
128 #ifdef CONFIG_NAND_FSL_ELBC
129 #define CONFIG_SYS_NAND_BASE 0xffa00000
130 #ifdef CONFIG_PHYS_64BIT
131 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
133 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
136 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
137 #define CONFIG_SYS_MAX_NAND_DEVICE 1
139 /* NAND flash config */
140 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
141 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
142 | BR_PS_8 /* Port Size = 8 bit */ \
143 | BR_MS_FCM /* MSEL = FCM */ \
145 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
146 | OR_FCM_PGS /* Large Page*/ \
153 #endif /* CONFIG_NAND_FSL_ELBC */
155 #define CONFIG_SYS_FLASH_EMPTY_INFO
156 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
158 #define CONFIG_HWCONFIG
160 /* define to use L1 as initial stack */
161 #define CONFIG_L1_INIT_RAM
162 #define CONFIG_SYS_INIT_RAM_LOCK
163 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
164 #ifdef CONFIG_PHYS_64BIT
165 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
166 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
167 /* The assembler doesn't like typecast */
168 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
169 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
170 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
174 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
176 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
178 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
180 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
182 /* Serial Port - controlled on board with jumper J8
186 #define CONFIG_SYS_NS16550_SERIAL
187 #define CONFIG_SYS_NS16550_REG_SIZE 1
188 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
190 #define CONFIG_SYS_BAUDRATE_TABLE \
191 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
193 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
194 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
195 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
196 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
203 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
204 #ifdef CONFIG_PHYS_64BIT
205 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
207 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
209 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
211 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
212 #ifdef CONFIG_PHYS_64BIT
213 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
215 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
217 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
220 * for slave u-boot IMAGE instored in master memory space,
221 * PHYS must be aligned based on the SIZE
223 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
224 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
225 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
226 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
228 * for slave UCODE and ENV instored in master memory space,
229 * PHYS must be aligned based on the SIZE
231 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
232 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
233 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
235 /* slave core release by master*/
236 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
237 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
240 * SRIO_PCIE_BOOT - SLAVE
242 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
243 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
244 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
245 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
249 * eSPI - Enhanced SPI
254 * Memory space is mapped 1-1, but I/O space must start from 0.
257 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
258 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
259 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
260 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
261 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
263 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
264 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
265 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
266 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
267 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
269 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
270 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
271 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
272 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
273 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
275 /* controller 4, Base address 203000 */
276 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
277 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
280 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
281 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
282 #ifdef CONFIG_PHYS_64BIT
283 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
285 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
287 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
288 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
289 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
290 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
291 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
292 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
293 CONFIG_SYS_BMAN_CENA_SIZE)
294 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
295 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
296 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
297 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
298 #ifdef CONFIG_PHYS_64BIT
299 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
301 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
303 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
304 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
305 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
306 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
307 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
308 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
309 CONFIG_SYS_QMAN_CENA_SIZE)
310 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
311 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
313 #define CONFIG_SYS_DPAA_FMAN
314 #define CONFIG_SYS_DPAA_PME
315 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
318 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
319 #endif /* CONFIG_PCI */
321 #ifdef CONFIG_FMAN_ENET
322 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
323 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
324 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
325 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
326 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
328 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
329 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
330 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
331 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
332 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
334 #define CONFIG_SYS_TBIPA_VALUE 8
340 #define CONFIG_LOADS_ECHO /* echo on for serial download */
341 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
344 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
345 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
349 * Miscellaneous configurable options
353 * For booting Linux, the board info and command line data
354 * have to be in the first 64 MB of memory, since this is
355 * the maximum mapped by the Linux kernel during initialization.
357 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
358 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
361 * Environment Configuration
363 #define CONFIG_ROOTPATH "/opt/nfsroot"
364 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
366 #ifdef CONFIG_TARGET_P4080DS
367 #define __USB_PHY_TYPE ulpi
369 #define __USB_PHY_TYPE utmi
372 #define CONFIG_EXTRA_ENV_SETTINGS \
373 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
374 "bank_intlv=cs0_cs1;" \
375 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
376 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
378 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
379 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
380 "tftpflash=tftpboot $loadaddr $uboot && " \
381 "protect off $ubootaddr +$filesize && " \
382 "erase $ubootaddr +$filesize && " \
383 "cp.b $loadaddr $ubootaddr $filesize && " \
384 "protect on $ubootaddr +$filesize && " \
385 "cmp.b $loadaddr $ubootaddr $filesize\0" \
386 "consoledev=ttyS0\0" \
387 "ramdiskaddr=2000000\0" \
388 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
389 "fdtaddr=1e00000\0" \
390 "fdtfile=p4080ds/p4080ds.dtb\0" \
393 #include <asm/fsl_secure_boot.h>
395 #endif /* __CONFIG_H */