1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * Corenet DS style board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
17 #ifdef CONFIG_RAMBOOT_PBL
18 #ifdef CONFIG_NXP_ESBC
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21 #ifdef CONFIG_MTD_RAW_NAND
22 #define CONFIG_RAMBOOT_NAND
24 #define CONFIG_BOOTSCRIPT_COPY_RAM
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
31 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
32 /* Set 1M boot space */
33 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
34 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
35 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
39 /* High Level Configuration Options */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
42 #ifndef CONFIG_RESET_VECTOR_ADDRESS
43 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
46 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
47 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
48 #define CONFIG_PCIE1 /* PCIE controller 1 */
49 #define CONFIG_PCIE2 /* PCIE controller 2 */
51 #if defined(CONFIG_SPIFLASH)
52 #elif defined(CONFIG_SDCARD)
53 #define CONFIG_FSL_FIXED_MMC_LOCATION
57 * These can be toggled for performance analysis, otherwise use default.
59 #define CONFIG_SYS_CACHE_STASHING
60 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
62 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
65 #define CONFIG_ENABLE_36BIT_PHYS
67 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
70 * Config the L3 Cache as L3 SRAM
72 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
73 #ifdef CONFIG_PHYS_64BIT
74 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
76 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
78 #define CONFIG_SYS_L3_SIZE (1024 << 10)
79 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
81 #ifdef CONFIG_PHYS_64BIT
82 #define CONFIG_SYS_DCSRBAR 0xf0000000
83 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
87 #define CONFIG_SYS_I2C_EEPROM_NXID
88 #define CONFIG_SYS_EEPROM_BUS_NUM 0
93 #define CONFIG_VERY_BIG_RAM
94 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
95 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
97 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
99 #define CONFIG_SYS_SPD_BUS_NUM 1
100 #define SPD_EEPROM_ADDRESS1 0x51
101 #define SPD_EEPROM_ADDRESS2 0x52
102 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
103 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
106 * Local Bus Definitions
109 /* Set the local bus clock 1/8 of platform clock */
110 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
112 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
113 #ifdef CONFIG_PHYS_64BIT
114 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
116 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
119 #define CONFIG_SYS_FLASH_BR_PRELIM \
120 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
122 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
123 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
125 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
126 #ifdef CONFIG_PHYS_64BIT
127 #define PIXIS_BASE_PHYS 0xfffdf0000ull
129 #define PIXIS_BASE_PHYS PIXIS_BASE
132 #define PIXIS_LBMAP_SWITCH 7
133 #define PIXIS_LBMAP_MASK 0xf0
134 #define PIXIS_LBMAP_SHIFT 4
135 #define PIXIS_LBMAP_ALTBANK 0x40
137 #define CONFIG_SYS_FLASH_QUIET_TEST
138 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
140 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
141 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
142 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
146 #if defined(CONFIG_RAMBOOT_PBL)
147 #define CONFIG_SYS_RAMBOOT
151 #ifdef CONFIG_NAND_FSL_ELBC
152 #define CONFIG_SYS_NAND_BASE 0xffa00000
153 #ifdef CONFIG_PHYS_64BIT
154 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
156 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
159 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
160 #define CONFIG_SYS_MAX_NAND_DEVICE 1
162 /* NAND flash config */
163 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
164 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
165 | BR_PS_8 /* Port Size = 8 bit */ \
166 | BR_MS_FCM /* MSEL = FCM */ \
168 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
169 | OR_FCM_PGS /* Large Page*/ \
176 #endif /* CONFIG_NAND_FSL_ELBC */
178 #define CONFIG_SYS_FLASH_EMPTY_INFO
179 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
181 #define CONFIG_HWCONFIG
183 /* define to use L1 as initial stack */
184 #define CONFIG_L1_INIT_RAM
185 #define CONFIG_SYS_INIT_RAM_LOCK
186 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
187 #ifdef CONFIG_PHYS_64BIT
188 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
189 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
190 /* The assembler doesn't like typecast */
191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
192 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
193 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
195 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
199 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
201 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
202 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
204 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
206 /* Serial Port - controlled on board with jumper J8
210 #define CONFIG_SYS_NS16550_SERIAL
211 #define CONFIG_SYS_NS16550_REG_SIZE 1
212 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
214 #define CONFIG_SYS_BAUDRATE_TABLE \
215 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
217 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
218 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
219 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
220 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
227 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
228 #ifdef CONFIG_PHYS_64BIT
229 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
231 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
233 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
235 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
236 #ifdef CONFIG_PHYS_64BIT
237 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
239 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
241 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
244 * for slave u-boot IMAGE instored in master memory space,
245 * PHYS must be aligned based on the SIZE
247 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
248 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
249 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
250 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
252 * for slave UCODE and ENV instored in master memory space,
253 * PHYS must be aligned based on the SIZE
255 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
256 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
257 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
259 /* slave core release by master*/
260 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
261 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
264 * SRIO_PCIE_BOOT - SLAVE
266 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
267 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
268 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
269 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
273 * eSPI - Enhanced SPI
278 * Memory space is mapped 1-1, but I/O space must start from 0.
281 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
282 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
283 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
284 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
285 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
287 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
288 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
289 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
290 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
291 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
293 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
294 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
295 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
296 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
297 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
299 /* controller 4, Base address 203000 */
300 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
301 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
304 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
305 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
306 #ifdef CONFIG_PHYS_64BIT
307 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
309 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
311 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
312 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
313 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
314 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
315 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
316 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
317 CONFIG_SYS_BMAN_CENA_SIZE)
318 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
319 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
320 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
321 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
322 #ifdef CONFIG_PHYS_64BIT
323 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
325 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
327 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
328 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
329 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
330 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
331 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
332 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
333 CONFIG_SYS_QMAN_CENA_SIZE)
334 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
335 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
337 #define CONFIG_SYS_DPAA_FMAN
338 #define CONFIG_SYS_DPAA_PME
339 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
342 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
343 #endif /* CONFIG_PCI */
346 #ifdef CONFIG_FSL_SATA_V2
348 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
349 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
351 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
352 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
357 #ifdef CONFIG_FMAN_ENET
358 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
359 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
360 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
361 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
362 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
364 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
365 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
366 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
367 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
368 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
370 #define CONFIG_SYS_TBIPA_VALUE 8
376 #define CONFIG_LOADS_ECHO /* echo on for serial download */
377 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
382 #define CONFIG_HAS_FSL_DR_USB
383 #define CONFIG_HAS_FSL_MPH_USB
385 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
386 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
390 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
391 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
395 * Miscellaneous configurable options
399 * For booting Linux, the board info and command line data
400 * have to be in the first 64 MB of memory, since this is
401 * the maximum mapped by the Linux kernel during initialization.
403 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
404 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
407 * Environment Configuration
409 #define CONFIG_ROOTPATH "/opt/nfsroot"
410 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
412 #ifdef CONFIG_TARGET_P4080DS
413 #define __USB_PHY_TYPE ulpi
415 #define __USB_PHY_TYPE utmi
418 #define CONFIG_EXTRA_ENV_SETTINGS \
419 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
420 "bank_intlv=cs0_cs1;" \
421 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
422 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
424 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
425 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
426 "tftpflash=tftpboot $loadaddr $uboot && " \
427 "protect off $ubootaddr +$filesize && " \
428 "erase $ubootaddr +$filesize && " \
429 "cp.b $loadaddr $ubootaddr $filesize && " \
430 "protect on $ubootaddr +$filesize && " \
431 "cmp.b $loadaddr $ubootaddr $filesize\0" \
432 "consoledev=ttyS0\0" \
433 "ramdiskaddr=2000000\0" \
434 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
435 "fdtaddr=1e00000\0" \
436 "fdtfile=p4080ds/p4080ds.dtb\0" \
439 #include <asm/fsl_secure_boot.h>
441 #endif /* __CONFIG_H */