include/configs/corenet_ds.h

   1 /*
   2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * Corenet DS style board configuration file
  25  */
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #include "../board/freescale/common/ics307_clk.h"
  30
  31 #ifdef CONFIG_RAMBOOT_PBL
  32 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  33 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  34 #endif
  35
  36 /* High Level Configuration Options */
  37 #define CONFIG_BOOKE
  38 #define CONFIG_E500                     /* BOOKE e500 family */
  39 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  40 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  41 #define CONFIG_MPC85xx                  /* MPC85xx/PQ3 platform */
  42 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  43 #define CONFIG_MP                       /* support multiple processors */
  44
  45 #ifndef CONFIG_SYS_TEXT_BASE
  46 #define CONFIG_SYS_TEXT_BASE    0xeff80000
  47 #endif
  48
  49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  50 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  51 #endif
  52
  53 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  54 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  55 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  56 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  57 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  58 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  59 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  60 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  61 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  62
  63 #define CONFIG_SYS_SRIO
  64 #define CONFIG_SRIO1                    /* SRIO port 1 */
  65 #define CONFIG_SRIO2                    /* SRIO port 2 */
  66
  67 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  68
  69 #define CONFIG_ENV_OVERWRITE
  70
  71 #if defined(CONFIG_RAMBOOT_PBL)
  72         #define CONFIG_SYS_NO_FLASH     /* Store ENV in memory only */
  73 #endif
  74
  75 #ifdef CONFIG_SYS_NO_FLASH
  76 #define CONFIG_ENV_IS_NOWHERE
  77 #else
  78 #define CONFIG_ENV_IS_IN_FLASH
  79 #define CONFIG_FLASH_CFI_DRIVER
  80 #define CONFIG_SYS_FLASH_CFI
  81 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  82 #endif
  83
  84 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
  85
  86 /*
  87  * These can be toggled for performance analysis, otherwise use default.
  88  */
  89 #define CONFIG_SYS_CACHE_STASHING
  90 #define CONFIG_BACKSIDE_L2_CACHE
  91 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  92 #define CONFIG_BTB                      /* toggle branch predition */
  93 #define CONFIG_DDR_ECC
  94 #ifdef CONFIG_DDR_ECC
  95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  96 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  97 #endif
  98
  99 #define CONFIG_ENABLE_36BIT_PHYS
 100
 101 #ifdef CONFIG_PHYS_64BIT
 102 #define CONFIG_ADDR_MAP
 103 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 104 #endif
 105
 106 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 107 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 108 #define CONFIG_SYS_MEMTEST_END          0x00400000
 109 #define CONFIG_SYS_ALT_MEMTEST
 110 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 111
 112 /*
 113  *  Config the L3 Cache as L3 SRAM
 114  */
 115 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 116 #ifdef CONFIG_PHYS_64BIT
 117 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 118 #else
 119 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 120 #endif
 121 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 122 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 123
 124 /*
 125  * Base addresses -- Note these are effective addresses where the
 126  * actual resources get mapped (not physical addresses)
 127  */
 128 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xfe000000      /* CCSRBAR Default */
 129 #define CONFIG_SYS_CCSRBAR              0xfe000000      /* relocated CCSRBAR */
 130 #ifdef CONFIG_PHYS_64BIT
 131 #define CONFIG_SYS_CCSRBAR_PHYS         0xffe000000ull  /* physical addr of CCSRBAR */
 132 #else
 133 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 134 #endif
 135 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 136
 137 #ifdef CONFIG_PHYS_64BIT
 138 #define CONFIG_SYS_DCSRBAR              0xf0000000
 139 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 140 #endif
 141
 142 /* EEPROM */
 143 #define CONFIG_ID_EEPROM
 144 #define CONFIG_SYS_I2C_EEPROM_NXID
 145 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 146 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 148
 149 /*
 150  * DDR Setup
 151  */
 152 #define CONFIG_VERY_BIG_RAM
 153 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 154 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 155
 156 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 157 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 158
 159 #define CONFIG_DDR_SPD
 160 #define CONFIG_FSL_DDR3
 161
 162 #define CONFIG_SYS_SPD_BUS_NUM  1
 163 #define SPD_EEPROM_ADDRESS1     0x51
 164 #define SPD_EEPROM_ADDRESS2     0x52
 165 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 166 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 167
 168 /*
 169  * Local Bus Definitions
 170  */
 171
 172 /* Set the local bus clock 1/8 of platform clock */
 173 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 174
 175 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 176 #ifdef CONFIG_PHYS_64BIT
 177 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 178 #else
 179 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 180 #endif
 181
 182 #define CONFIG_SYS_BR0_PRELIM \
 183         (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
 184          BR_PS_16 | BR_V)
 185 #define CONFIG_SYS_OR0_PRELIM   ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 186                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 187
 188 #define CONFIG_SYS_BR1_PRELIM \
 189         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 190 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 191
 192 #define CONFIG_FSL_NGPIXIS              /* use common ngPIXIS code */
 193 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 194 #ifdef CONFIG_PHYS_64BIT
 195 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 196 #else
 197 #define PIXIS_BASE_PHYS         PIXIS_BASE
 198 #endif
 199
 200 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 201 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 202
 203 #define PIXIS_LBMAP_SWITCH      7
 204 #define PIXIS_LBMAP_MASK        0xf0
 205 #define PIXIS_LBMAP_SHIFT       4
 206 #define PIXIS_LBMAP_ALTBANK     0x40
 207
 208 #define CONFIG_SYS_FLASH_QUIET_TEST
 209 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 210
 211 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 212 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 213 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 214 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 215
 216 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 217
 218 #if defined(CONFIG_RAMBOOT_PBL)
 219 #define CONFIG_SYS_RAMBOOT
 220 #endif
 221
 222 /* Nand Flash */
 223 #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
 224 #define CONFIG_NAND_FSL_ELBC
 225 #ifdef CONFIG_NAND_FSL_ELBC
 226 #define CONFIG_SYS_NAND_BASE            0xffa00000
 227 #ifdef CONFIG_PHYS_64BIT
 228 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 229 #else
 230 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 231 #endif
 232
 233 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 234 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 235 #define CONFIG_MTD_NAND_VERIFY_WRITE
 236 #define CONFIG_CMD_NAND
 237 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 238
 239 /* NAND flash config */
 240 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 241                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 242                                | BR_PS_8               /* Port Size = 8 bit */ \
 243                                | BR_MS_FCM             /* MSEL = FCM */ \
 244                                | BR_V)                 /* valid */
 245 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 246                                | OR_FCM_PGS            /* Large Page*/ \
 247                                | OR_FCM_CSCT \
 248                                | OR_FCM_CST \
 249                                | OR_FCM_CHT \
 250                                | OR_FCM_SCY_1 \
 251                                | OR_FCM_TRLX \
 252                                | OR_FCM_EHTR)
 253
 254 #define CONFIG_SYS_BR2_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 255 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 256 #endif /* CONFIG_NAND_FSL_ELBC */
 257 #endif
 258
 259 #define CONFIG_SYS_FLASH_EMPTY_INFO
 260 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 261 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 262
 263 #define CONFIG_BOARD_EARLY_INIT_F
 264 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 265 #define CONFIG_MISC_INIT_R
 266
 267 #define CONFIG_HWCONFIG
 268
 269 /* define to use L1 as initial stack */
 270 #define CONFIG_L1_INIT_RAM
 271 #define CONFIG_SYS_INIT_RAM_LOCK
 272 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 273 #ifdef CONFIG_PHYS_64BIT
 274 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 275 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 276 /* The assembler doesn't like typecast */
 277 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 278         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 279           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 280 #else
 281 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 282 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 283 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 284 #endif
 285 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 286
 287 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 288 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 289
 290 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 291 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 292
 293 /* Serial Port - controlled on board with jumper J8
 294  * open - index 2
 295  * shorted - index 1
 296  */
 297 #define CONFIG_CONS_INDEX       1
 298 #define CONFIG_SYS_NS16550
 299 #define CONFIG_SYS_NS16550_SERIAL
 300 #define CONFIG_SYS_NS16550_REG_SIZE     1
 301 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 302
 303 #define CONFIG_SYS_BAUDRATE_TABLE       \
 304         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 305
 306 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 307 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 308 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 309 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 310
 311 /* Use the HUSH parser */
 312 #define CONFIG_SYS_HUSH_PARSER
 313 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 314
 315 /* pass open firmware flat tree */
 316 #define CONFIG_OF_LIBFDT
 317 #define CONFIG_OF_BOARD_SETUP
 318 #define CONFIG_OF_STDOUT_VIA_ALIAS
 319
 320 /* new uImage format support */
 321 #define CONFIG_FIT
 322 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 323
 324 /* I2C */
 325 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 326 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 327 #define CONFIG_I2C_MULTI_BUS
 328 #define CONFIG_I2C_CMD_TREE
 329 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 330 #define CONFIG_SYS_I2C_SLAVE            0x7F
 331 #define CONFIG_SYS_I2C_OFFSET           0x118000
 332 #define CONFIG_SYS_I2C2_OFFSET          0x118100
 333
 334 /*
 335  * RapidIO
 336  */
 337 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 338 #ifdef CONFIG_PHYS_64BIT
 339 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 340 #else
 341 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 342 #endif
 343 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 344
 345 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 346 #ifdef CONFIG_PHYS_64BIT
 347 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 348 #else
 349 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 350 #endif
 351 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 352
 353 /*
 354  * eSPI - Enhanced SPI
 355  */
 356 #define CONFIG_FSL_ESPI
 357 #define CONFIG_SPI_FLASH
 358 #define CONFIG_SPI_FLASH_SPANSION
 359 #define CONFIG_CMD_SF
 360 #define CONFIG_SF_DEFAULT_SPEED         10000000
 361 #define CONFIG_SF_DEFAULT_MODE          0
 362
 363 /*
 364  * General PCI
 365  * Memory space is mapped 1-1, but I/O space must start from 0.
 366  */
 367
 368 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 369 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 370 #ifdef CONFIG_PHYS_64BIT
 371 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 372 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 373 #else
 374 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 375 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 376 #endif
 377 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 378 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 379 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 380 #ifdef CONFIG_PHYS_64BIT
 381 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 382 #else
 383 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 384 #endif
 385 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 386
 387 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 388 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 389 #ifdef CONFIG_PHYS_64BIT
 390 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 391 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 392 #else
 393 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 394 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 395 #endif
 396 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 397 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 398 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 399 #ifdef CONFIG_PHYS_64BIT
 400 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 401 #else
 402 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 403 #endif
 404 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 405
 406 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 407 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 408 #ifdef CONFIG_PHYS_64BIT
 409 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 410 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 411 #else
 412 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 413 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 414 #endif
 415 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 416 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 417 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 418 #ifdef CONFIG_PHYS_64BIT
 419 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 420 #else
 421 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 422 #endif
 423 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 424
 425 /* controller 4, Base address 203000 */
 426 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 427 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 428 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 429 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 430 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 431 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 432
 433 /* Qman/Bman */
 434 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 435 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 436 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 437 #ifdef CONFIG_PHYS_64BIT
 438 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 439 #else
 440 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 441 #endif
 442 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 443 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 444 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 445 #ifdef CONFIG_PHYS_64BIT
 446 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 447 #else
 448 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 449 #endif
 450 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 451
 452 #define CONFIG_SYS_DPAA_FMAN
 453 #define CONFIG_SYS_DPAA_PME
 454 /* Default address of microcode for the Linux Fman driver */
 455 #define CONFIG_SYS_FMAN_FW_ADDR         0xEF000000
 456 #ifdef CONFIG_PHYS_64BIT
 457 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS    0xFEF000000ULL
 458 #else
 459 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS    CONFIG_SYS_FMAN_FW_ADDR
 460 #endif
 461
 462 #ifdef CONFIG_SYS_DPAA_FMAN
 463 #define CONFIG_FMAN_ENET
 464 #endif
 465
 466 #ifdef CONFIG_PCI
 467 #define CONFIG_NET_MULTI
 468 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 469 #define CONFIG_E1000
 470
 471 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 472 #define CONFIG_DOS_PARTITION
 473 #endif  /* CONFIG_PCI */
 474
 475 /* SATA */
 476 #ifdef CONFIG_FSL_SATA_V2
 477 #define CONFIG_LIBATA
 478 #define CONFIG_FSL_SATA
 479
 480 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 481 #define CONFIG_SATA1
 482 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 483 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 484 #define CONFIG_SATA2
 485 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 486 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 487
 488 #define CONFIG_LBA48
 489 #define CONFIG_CMD_SATA
 490 #define CONFIG_DOS_PARTITION
 491 #define CONFIG_CMD_EXT2
 492 #endif
 493
 494 #ifdef CONFIG_FMAN_ENET
 495 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 496 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 497 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 498 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 499 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 500
 501 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 502 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 503 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 504 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 505 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 506
 507 #define CONFIG_SYS_TBIPA_VALUE  8
 508 #define CONFIG_MII              /* MII PHY management */
 509 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 510 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 511 #endif
 512
 513 /*
 514  * Environment
 515  */
 516 #define CONFIG_ENV_SIZE         0x2000
 517 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 518
 519 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 520 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 521
 522 /*
 523  * Command line configuration.
 524  */
 525 #include <config_cmd_default.h>
 526
 527 #define CONFIG_CMD_DHCP
 528 #define CONFIG_CMD_ELF
 529 #define CONFIG_CMD_ERRATA
 530 #define CONFIG_CMD_GREPENV
 531 #define CONFIG_CMD_IRQ
 532 #define CONFIG_CMD_I2C
 533 #define CONFIG_CMD_MII
 534 #define CONFIG_CMD_PING
 535 #define CONFIG_CMD_SETEXPR
 536
 537 #ifdef CONFIG_PCI
 538 #define CONFIG_CMD_PCI
 539 #define CONFIG_CMD_NET
 540 #endif
 541
 542 /*
 543 * USB
 544 */
 545 #define CONFIG_CMD_USB
 546 #define CONFIG_USB_STORAGE
 547 #define CONFIG_USB_EHCI
 548 #define CONFIG_USB_EHCI_FSL
 549 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 550 #define CONFIG_CMD_EXT2
 551
 552 #define CONFIG_MMC
 553
 554 #ifdef CONFIG_MMC
 555 #define CONFIG_FSL_ESDHC
 556 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 557 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 558 #define CONFIG_CMD_MMC
 559 #define CONFIG_GENERIC_MMC
 560 #define CONFIG_CMD_EXT2
 561 #define CONFIG_CMD_FAT
 562 #define CONFIG_DOS_PARTITION
 563 #endif
 564
 565 /*
 566  * Miscellaneous configurable options
 567  */
 568 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 569 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 570 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 571 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 572 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 573 #ifdef CONFIG_CMD_KGDB
 574 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 575 #else
 576 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 577 #endif
 578 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 579 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 580 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 581 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 582
 583 /*
 584  * For booting Linux, the board info and command line data
 585  * have to be in the first 64 MB of memory, since this is
 586  * the maximum mapped by the Linux kernel during initialization.
 587  */
 588 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 589 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 590
 591 #ifdef CONFIG_CMD_KGDB
 592 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 593 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 594 #endif
 595
 596 /*
 597  * Environment Configuration
 598  */
 599 #define CONFIG_ROOTPATH         /opt/nfsroot
 600 #define CONFIG_BOOTFILE         uImage
 601 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 602
 603 /* default location for tftp and bootm */
 604 #define CONFIG_LOADADDR         1000000
 605
 606 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 607
 608 #define CONFIG_BAUDRATE 115200
 609
 610 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 611         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 612         "bank_intlv=cs0_cs1\0"                                  \
 613         "netdev=eth0\0"                                         \
 614         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                  \
 615         "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"                  \
 616         "tftpflash=tftpboot $loadaddr $uboot && "               \
 617         "protect off $ubootaddr +$filesize && "                 \
 618         "erase $ubootaddr +$filesize && "                       \
 619         "cp.b $loadaddr $ubootaddr $filesize && "               \
 620         "protect on $ubootaddr +$filesize && "                  \
 621         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 622         "consoledev=ttyS0\0"                                    \
 623         "ramdiskaddr=2000000\0"                                 \
 624         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 625         "fdtaddr=c00000\0"                                      \
 626         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 627         "bdev=sda3\0"                                           \
 628         "c=ffe\0"                                               \
 629         "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0"
 630
 631 #define CONFIG_HDBOOT                                   \
 632         "setenv bootargs root=/dev/$bdev rw "           \
 633         "console=$consoledev,$baudrate $othbootargs;"   \
 634         "tftp $loadaddr $bootfile;"                     \
 635         "tftp $fdtaddr $fdtfile;"                       \
 636         "bootm $loadaddr - $fdtaddr"
 637
 638 #define CONFIG_NFSBOOTCOMMAND                   \
 639         "setenv bootargs root=/dev/nfs rw "     \
 640         "nfsroot=$serverip:$rootpath "          \
 641         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 642         "console=$consoledev,$baudrate $othbootargs;"   \
 643         "tftp $loadaddr $bootfile;"             \
 644         "tftp $fdtaddr $fdtfile;"               \
 645         "bootm $loadaddr - $fdtaddr"
 646
 647 #define CONFIG_RAMBOOTCOMMAND                           \
 648         "setenv bootargs root=/dev/ram rw "             \
 649         "console=$consoledev,$baudrate $othbootargs;"   \
 650         "tftp $ramdiskaddr $ramdiskfile;"               \
 651         "tftp $loadaddr $bootfile;"                     \
 652         "tftp $fdtaddr $fdtfile;"                       \
 653         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 654
 655 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 656
 657 #endif  /* __CONFIG_H */