include/configs/corenet_ds.h

   1 /*
   2  * Copyright 2009-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_DISPLAY_BOARDINFO
  14
  15 #include "../board/freescale/common/ics307_clk.h"
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #ifdef CONFIG_SECURE_BOOT
  19 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  21 #ifdef CONFIG_NAND
  22 #define CONFIG_RAMBOOT_NAND
  23 #endif
  24 #define CONFIG_BOOTSCRIPT_COPY_RAM
  25 #else
  26 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  28 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
  29 #if defined(CONFIG_P3041DS)
  30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
  31 #elif defined(CONFIG_P4080DS)
  32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
  33 #elif defined(CONFIG_P5020DS)
  34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
  35 #elif defined(CONFIG_P5040DS)
  36 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
  37 #endif
  38 #endif
  39 #endif
  40
  41 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  42 /* Set 1M boot space */
  43 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  44 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  45                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  46 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  47 #define CONFIG_SYS_NO_FLASH
  48 #endif
  49
  50 /* High Level Configuration Options */
  51 #define CONFIG_BOOKE
  52 #define CONFIG_E500                     /* BOOKE e500 family */
  53 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  54 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  55 #define CONFIG_MP                       /* support multiple processors */
  56
  57 #ifndef CONFIG_SYS_TEXT_BASE
  58 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  59 #endif
  60
  61 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  62 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  63 #endif
  64
  65 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  66 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  67 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  68 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  69 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  70 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  71 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  72 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  73 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  74
  75 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  76
  77 #define CONFIG_ENV_OVERWRITE
  78
  79 #ifdef CONFIG_SYS_NO_FLASH
  80 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  81 #define CONFIG_ENV_IS_NOWHERE
  82 #endif
  83 #else
  84 #define CONFIG_FLASH_CFI_DRIVER
  85 #define CONFIG_SYS_FLASH_CFI
  86 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  87 #endif
  88
  89 #if defined(CONFIG_SPIFLASH)
  90 #define CONFIG_SYS_EXTRA_ENV_RELOC
  91 #define CONFIG_ENV_IS_IN_SPI_FLASH
  92 #define CONFIG_ENV_SPI_BUS              0
  93 #define CONFIG_ENV_SPI_CS               0
  94 #define CONFIG_ENV_SPI_MAX_HZ           10000000
  95 #define CONFIG_ENV_SPI_MODE             0
  96 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  97 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  98 #define CONFIG_ENV_SECT_SIZE            0x10000
  99 #elif defined(CONFIG_SDCARD)
 100 #define CONFIG_SYS_EXTRA_ENV_RELOC
 101 #define CONFIG_ENV_IS_IN_MMC
 102 #define CONFIG_FSL_FIXED_MMC_LOCATION
 103 #define CONFIG_SYS_MMC_ENV_DEV          0
 104 #define CONFIG_ENV_SIZE                 0x2000
 105 #define CONFIG_ENV_OFFSET               (512 * 1658)
 106 #elif defined(CONFIG_NAND)
 107 #define CONFIG_SYS_EXTRA_ENV_RELOC
 108 #define CONFIG_ENV_IS_IN_NAND
 109 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
 110 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
 111 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 112 #define CONFIG_ENV_IS_IN_REMOTE
 113 #define CONFIG_ENV_ADDR         0xffe20000
 114 #define CONFIG_ENV_SIZE         0x2000
 115 #elif defined(CONFIG_ENV_IS_NOWHERE)
 116 #define CONFIG_ENV_SIZE         0x2000
 117 #else
 118 #define CONFIG_ENV_IS_IN_FLASH
 119 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 120 #define CONFIG_ENV_SIZE         0x2000
 121 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 122 #endif
 123
 124 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 125
 126 /*
 127  * These can be toggled for performance analysis, otherwise use default.
 128  */
 129 #define CONFIG_SYS_CACHE_STASHING
 130 #define CONFIG_BACKSIDE_L2_CACHE
 131 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
 132 #define CONFIG_BTB                      /* toggle branch predition */
 133 #define CONFIG_DDR_ECC
 134 #ifdef CONFIG_DDR_ECC
 135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 136 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 137 #endif
 138
 139 #define CONFIG_ENABLE_36BIT_PHYS
 140
 141 #ifdef CONFIG_PHYS_64BIT
 142 #define CONFIG_ADDR_MAP
 143 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 144 #endif
 145
 146 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 147 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 148 #define CONFIG_SYS_MEMTEST_END          0x00400000
 149 #define CONFIG_SYS_ALT_MEMTEST
 150 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 151
 152 /*
 153  *  Config the L3 Cache as L3 SRAM
 154  */
 155 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 156 #ifdef CONFIG_PHYS_64BIT
 157 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 158 #else
 159 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 160 #endif
 161 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 162 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 163
 164 #ifdef CONFIG_PHYS_64BIT
 165 #define CONFIG_SYS_DCSRBAR              0xf0000000
 166 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 167 #endif
 168
 169 /* EEPROM */
 170 #define CONFIG_ID_EEPROM
 171 #define CONFIG_SYS_I2C_EEPROM_NXID
 172 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 175
 176 /*
 177  * DDR Setup
 178  */
 179 #define CONFIG_VERY_BIG_RAM
 180 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 181 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 182
 183 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 184 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 185
 186 #define CONFIG_DDR_SPD
 187 #define CONFIG_SYS_FSL_DDR3
 188
 189 #define CONFIG_SYS_SPD_BUS_NUM  1
 190 #define SPD_EEPROM_ADDRESS1     0x51
 191 #define SPD_EEPROM_ADDRESS2     0x52
 192 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 193 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 194
 195 /*
 196  * Local Bus Definitions
 197  */
 198
 199 /* Set the local bus clock 1/8 of platform clock */
 200 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
 201
 202 #define CONFIG_SYS_FLASH_BASE           0xe0000000      /* Start of PromJet */
 203 #ifdef CONFIG_PHYS_64BIT
 204 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
 205 #else
 206 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 207 #endif
 208
 209 #define CONFIG_SYS_FLASH_BR_PRELIM \
 210                 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
 211                  | BR_PS_16 | BR_V)
 212 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
 213                                         | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
 214
 215 #define CONFIG_SYS_BR1_PRELIM \
 216         (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 217 #define CONFIG_SYS_OR1_PRELIM   0xf8000ff7
 218
 219 #define PIXIS_BASE              0xffdf0000      /* PIXIS registers */
 220 #ifdef CONFIG_PHYS_64BIT
 221 #define PIXIS_BASE_PHYS         0xfffdf0000ull
 222 #else
 223 #define PIXIS_BASE_PHYS         PIXIS_BASE
 224 #endif
 225
 226 #define CONFIG_SYS_BR3_PRELIM   (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 227 #define CONFIG_SYS_OR3_PRELIM   0xffffeff7      /* 32KB but only 4k mapped */
 228
 229 #define PIXIS_LBMAP_SWITCH      7
 230 #define PIXIS_LBMAP_MASK        0xf0
 231 #define PIXIS_LBMAP_SHIFT       4
 232 #define PIXIS_LBMAP_ALTBANK     0x40
 233
 234 #define CONFIG_SYS_FLASH_QUIET_TEST
 235 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 236
 237 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 238 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 239 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 240 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 241
 242 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 243
 244 #if defined(CONFIG_RAMBOOT_PBL)
 245 #define CONFIG_SYS_RAMBOOT
 246 #endif
 247
 248 /* Nand Flash */
 249 #ifdef CONFIG_NAND_FSL_ELBC
 250 #define CONFIG_SYS_NAND_BASE            0xffa00000
 251 #ifdef CONFIG_PHYS_64BIT
 252 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 253 #else
 254 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 255 #endif
 256
 257 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 258 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 259 #define CONFIG_CMD_NAND
 260 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 261
 262 /* NAND flash config */
 263 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 264                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 265                                | BR_PS_8               /* Port Size = 8 bit */ \
 266                                | BR_MS_FCM             /* MSEL = FCM */ \
 267                                | BR_V)                 /* valid */
 268 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 269                                | OR_FCM_PGS            /* Large Page*/ \
 270                                | OR_FCM_CSCT \
 271                                | OR_FCM_CST \
 272                                | OR_FCM_CHT \
 273                                | OR_FCM_SCY_1 \
 274                                | OR_FCM_TRLX \
 275                                | OR_FCM_EHTR)
 276
 277 #ifdef CONFIG_NAND
 278 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 279 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 280 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 281 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 282 #else
 283 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 284 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 285 #define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 286 #define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 287 #endif
 288 #else
 289 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
 290 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
 291 #endif /* CONFIG_NAND_FSL_ELBC */
 292
 293 #define CONFIG_SYS_FLASH_EMPTY_INFO
 294 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 295 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 296
 297 #define CONFIG_BOARD_EARLY_INIT_F
 298 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 299 #define CONFIG_MISC_INIT_R
 300
 301 #define CONFIG_HWCONFIG
 302
 303 /* define to use L1 as initial stack */
 304 #define CONFIG_L1_INIT_RAM
 305 #define CONFIG_SYS_INIT_RAM_LOCK
 306 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 307 #ifdef CONFIG_PHYS_64BIT
 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 310 /* The assembler doesn't like typecast */
 311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 312         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 313           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 314 #else
 315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 318 #endif
 319 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 320
 321 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 322 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 323
 324 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 325 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 326
 327 /* Serial Port - controlled on board with jumper J8
 328  * open - index 2
 329  * shorted - index 1
 330  */
 331 #define CONFIG_CONS_INDEX       1
 332 #define CONFIG_SYS_NS16550_SERIAL
 333 #define CONFIG_SYS_NS16550_REG_SIZE     1
 334 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 335
 336 #define CONFIG_SYS_BAUDRATE_TABLE       \
 337         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 338
 339 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 340 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 341 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 342 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 343
 344 /* Use the HUSH parser */
 345 #define CONFIG_SYS_HUSH_PARSER
 346
 347 /* pass open firmware flat tree */
 348 #define CONFIG_OF_BOARD_SETUP
 349 #define CONFIG_OF_STDOUT_VIA_ALIAS
 350
 351 /* new uImage format support */
 352 #define CONFIG_FIT
 353 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 354
 355 /* I2C */
 356 #define CONFIG_SYS_I2C
 357 #define CONFIG_SYS_I2C_FSL
 358 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 359 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 360 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 361 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 362 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 363 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 364
 365 /*
 366  * RapidIO
 367  */
 368 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 369 #ifdef CONFIG_PHYS_64BIT
 370 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 371 #else
 372 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 373 #endif
 374 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 375
 376 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 377 #ifdef CONFIG_PHYS_64BIT
 378 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 379 #else
 380 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 381 #endif
 382 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 383
 384 /*
 385  * for slave u-boot IMAGE instored in master memory space,
 386  * PHYS must be aligned based on the SIZE
 387  */
 388 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 389 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 390 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 391 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 392 /*
 393  * for slave UCODE and ENV instored in master memory space,
 394  * PHYS must be aligned based on the SIZE
 395  */
 396 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 397 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 398 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 399
 400 /* slave core release by master*/
 401 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 402 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 403
 404 /*
 405  * SRIO_PCIE_BOOT - SLAVE
 406  */
 407 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 408 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 409 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 410                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 411 #endif
 412
 413 /*
 414  * eSPI - Enhanced SPI
 415  */
 416 #define CONFIG_CMD_SF
 417 #define CONFIG_SF_DEFAULT_SPEED         10000000
 418 #define CONFIG_SF_DEFAULT_MODE          0
 419
 420 /*
 421  * General PCI
 422  * Memory space is mapped 1-1, but I/O space must start from 0.
 423  */
 424
 425 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 426 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 427 #ifdef CONFIG_PHYS_64BIT
 428 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 429 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 430 #else
 431 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 432 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 433 #endif
 434 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 435 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 436 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 437 #ifdef CONFIG_PHYS_64BIT
 438 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 439 #else
 440 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 441 #endif
 442 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 443
 444 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 445 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 446 #ifdef CONFIG_PHYS_64BIT
 447 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 448 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 449 #else
 450 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 451 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 452 #endif
 453 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 454 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 455 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 456 #ifdef CONFIG_PHYS_64BIT
 457 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 458 #else
 459 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 460 #endif
 461 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 462
 463 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 464 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 465 #ifdef CONFIG_PHYS_64BIT
 466 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 467 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 468 #else
 469 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 470 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 471 #endif
 472 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 473 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 474 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 475 #ifdef CONFIG_PHYS_64BIT
 476 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 477 #else
 478 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 479 #endif
 480 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 481
 482 /* controller 4, Base address 203000 */
 483 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 484 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 485 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 486 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 487 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 488 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 489
 490 /* Qman/Bman */
 491 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 492 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 493 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 494 #ifdef CONFIG_PHYS_64BIT
 495 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 496 #else
 497 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 498 #endif
 499 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 500 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 501 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 502 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 503 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 504 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 505                                         CONFIG_SYS_BMAN_CENA_SIZE)
 506 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 507 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 508 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 509 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 510 #ifdef CONFIG_PHYS_64BIT
 511 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 512 #else
 513 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 514 #endif
 515 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 516 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 517 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 518 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 519 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 520 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 521                                         CONFIG_SYS_QMAN_CENA_SIZE)
 522 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 523 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 524
 525 #define CONFIG_SYS_DPAA_FMAN
 526 #define CONFIG_SYS_DPAA_PME
 527 /* Default address of microcode for the Linux Fman driver */
 528 #if defined(CONFIG_SPIFLASH)
 529 /*
 530  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 531  * env, so we got 0x110000.
 532  */
 533 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 534 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 535 #elif defined(CONFIG_SDCARD)
 536 /*
 537  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 538  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 539  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 540  */
 541 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 542 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 543 #elif defined(CONFIG_NAND)
 544 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 545 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 546 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 547 /*
 548  * Slave has no ucode locally, it can fetch this from remote. When implementing
 549  * in two corenet boards, slave's ucode could be stored in master's memory
 550  * space, the address can be mapped from slave TLB->slave LAW->
 551  * slave SRIO or PCIE outbound window->master inbound window->
 552  * master LAW->the ucode address in master's memory space.
 553  */
 554 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 555 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 556 #else
 557 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 558 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 559 #endif
 560 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 561 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 562
 563 #ifdef CONFIG_SYS_DPAA_FMAN
 564 #define CONFIG_FMAN_ENET
 565 #define CONFIG_PHYLIB_10G
 566 #define CONFIG_PHY_VITESSE
 567 #define CONFIG_PHY_TERANETICS
 568 #endif
 569
 570 #ifdef CONFIG_PCI
 571 #define CONFIG_PCI_INDIRECT_BRIDGE
 572 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 573
 574 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 575 #define CONFIG_DOS_PARTITION
 576 #endif  /* CONFIG_PCI */
 577
 578 /* SATA */
 579 #ifdef CONFIG_FSL_SATA_V2
 580 #define CONFIG_LIBATA
 581 #define CONFIG_FSL_SATA
 582
 583 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 584 #define CONFIG_SATA1
 585 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 586 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 587 #define CONFIG_SATA2
 588 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 589 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 590
 591 #define CONFIG_LBA48
 592 #define CONFIG_CMD_SATA
 593 #define CONFIG_DOS_PARTITION
 594 #define CONFIG_CMD_EXT2
 595 #endif
 596
 597 #ifdef CONFIG_FMAN_ENET
 598 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x1c
 599 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x1d
 600 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x1e
 601 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1f
 602 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  4
 603
 604 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR  0x1c
 605 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR  0x1d
 606 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR  0x1e
 607 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR  0x1f
 608 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR  0
 609
 610 #define CONFIG_SYS_TBIPA_VALUE  8
 611 #define CONFIG_MII              /* MII PHY management */
 612 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 613 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 614 #endif
 615
 616 /*
 617  * Environment
 618  */
 619 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 620 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 621
 622 /*
 623  * Command line configuration.
 624  */
 625 #define CONFIG_CMD_DHCP
 626 #define CONFIG_CMD_ERRATA
 627 #define CONFIG_CMD_GREPENV
 628 #define CONFIG_CMD_IRQ
 629 #define CONFIG_CMD_I2C
 630 #define CONFIG_CMD_MII
 631 #define CONFIG_CMD_PING
 632 #define CONFIG_CMD_REGINFO
 633
 634 #ifdef CONFIG_PCI
 635 #define CONFIG_CMD_PCI
 636 #endif
 637
 638 /*
 639 * USB
 640 */
 641 #define CONFIG_HAS_FSL_DR_USB
 642 #define CONFIG_HAS_FSL_MPH_USB
 643
 644 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 645 #define CONFIG_CMD_USB
 646 #define CONFIG_USB_STORAGE
 647 #define CONFIG_USB_EHCI
 648 #define CONFIG_USB_EHCI_FSL
 649 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 650 #define CONFIG_CMD_EXT2
 651 #endif
 652
 653 #ifdef CONFIG_MMC
 654 #define CONFIG_FSL_ESDHC
 655 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 656 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 657 #define CONFIG_CMD_MMC
 658 #define CONFIG_GENERIC_MMC
 659 #define CONFIG_CMD_EXT2
 660 #define CONFIG_CMD_FAT
 661 #define CONFIG_DOS_PARTITION
 662 #endif
 663
 664 /* Hash command with SHA acceleration supported in hardware */
 665 #ifdef CONFIG_FSL_CAAM
 666 #define CONFIG_CMD_HASH
 667 #define CONFIG_SHA_HW_ACCEL
 668 #endif
 669
 670 /*
 671  * Miscellaneous configurable options
 672  */
 673 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 674 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 675 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 676 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 677 #ifdef CONFIG_CMD_KGDB
 678 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 679 #else
 680 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 681 #endif
 682 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 683 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 684 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 685
 686 /*
 687  * For booting Linux, the board info and command line data
 688  * have to be in the first 64 MB of memory, since this is
 689  * the maximum mapped by the Linux kernel during initialization.
 690  */
 691 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 692 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 693
 694 #ifdef CONFIG_CMD_KGDB
 695 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 696 #endif
 697
 698 /*
 699  * Environment Configuration
 700  */
 701 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 702 #define CONFIG_BOOTFILE         "uImage"
 703 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 704
 705 /* default location for tftp and bootm */
 706 #define CONFIG_LOADADDR         1000000
 707
 708 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
 709
 710 #define CONFIG_BAUDRATE 115200
 711
 712 #ifdef CONFIG_P4080DS
 713 #define __USB_PHY_TYPE  ulpi
 714 #else
 715 #define __USB_PHY_TYPE  utmi
 716 #endif
 717
 718 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 719         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 720         "bank_intlv=cs0_cs1;"                                   \
 721         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 722         "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 723         "netdev=eth0\0"                                         \
 724         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 725         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 726         "tftpflash=tftpboot $loadaddr $uboot && "               \
 727         "protect off $ubootaddr +$filesize && "                 \
 728         "erase $ubootaddr +$filesize && "                       \
 729         "cp.b $loadaddr $ubootaddr $filesize && "               \
 730         "protect on $ubootaddr +$filesize && "                  \
 731         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 732         "consoledev=ttyS0\0"                                    \
 733         "ramdiskaddr=2000000\0"                                 \
 734         "ramdiskfile=p4080ds/ramdisk.uboot\0"                   \
 735         "fdtaddr=c00000\0"                                      \
 736         "fdtfile=p4080ds/p4080ds.dtb\0"                         \
 737         "bdev=sda3\0"
 738
 739 #define CONFIG_HDBOOT                                   \
 740         "setenv bootargs root=/dev/$bdev rw "           \
 741         "console=$consoledev,$baudrate $othbootargs;"   \
 742         "tftp $loadaddr $bootfile;"                     \
 743         "tftp $fdtaddr $fdtfile;"                       \
 744         "bootm $loadaddr - $fdtaddr"
 745
 746 #define CONFIG_NFSBOOTCOMMAND                   \
 747         "setenv bootargs root=/dev/nfs rw "     \
 748         "nfsroot=$serverip:$rootpath "          \
 749         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 750         "console=$consoledev,$baudrate $othbootargs;"   \
 751         "tftp $loadaddr $bootfile;"             \
 752         "tftp $fdtaddr $fdtfile;"               \
 753         "bootm $loadaddr - $fdtaddr"
 754
 755 #define CONFIG_RAMBOOTCOMMAND                           \
 756         "setenv bootargs root=/dev/ram rw "             \
 757         "console=$consoledev,$baudrate $othbootargs;"   \
 758         "tftp $ramdiskaddr $ramdiskfile;"               \
 759         "tftp $loadaddr $bootfile;"                     \
 760         "tftp $fdtaddr $fdtfile;"                       \
 761         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 762
 763 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 764
 765 #include <asm/fsl_secure_boot.h>
 766
 767 #endif  /* __CONFIG_H */