1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020-2021 NXP
8 * Corenet DS style board configuration file
13 #include <linux/stringify.h>
15 #include "../board/freescale/common/ics307_clk.h"
17 #ifdef CONFIG_RAMBOOT_PBL
18 #ifdef CONFIG_NXP_ESBC
19 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
21 #ifdef CONFIG_MTD_RAW_NAND
22 #define CONFIG_RAMBOOT_NAND
24 #define CONFIG_BOOTSCRIPT_COPY_RAM
26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
31 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
32 /* Set 1M boot space */
33 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
34 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
35 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
36 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
39 /* High Level Configuration Options */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
42 #ifndef CONFIG_RESET_VECTOR_ADDRESS
43 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
46 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
47 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
48 #define CONFIG_PCIE1 /* PCIE controller 1 */
49 #define CONFIG_PCIE2 /* PCIE controller 2 */
51 #if defined(CONFIG_SPIFLASH)
52 #elif defined(CONFIG_SDCARD)
53 #define CONFIG_FSL_FIXED_MMC_LOCATION
57 * These can be toggled for performance analysis, otherwise use default.
59 #define CONFIG_SYS_CACHE_STASHING
60 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
62 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
65 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
68 * Config the L3 Cache as L3 SRAM
70 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
71 #ifdef CONFIG_PHYS_64BIT
72 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
74 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
76 #define CONFIG_SYS_L3_SIZE (1024 << 10)
77 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
79 #ifdef CONFIG_PHYS_64BIT
80 #define CONFIG_SYS_DCSRBAR 0xf0000000
81 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
85 #define CONFIG_SYS_I2C_EEPROM_NXID
86 #define CONFIG_SYS_EEPROM_BUS_NUM 0
91 #define CONFIG_VERY_BIG_RAM
92 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
95 #define CONFIG_SYS_SPD_BUS_NUM 1
96 #define SPD_EEPROM_ADDRESS1 0x51
97 #define SPD_EEPROM_ADDRESS2 0x52
98 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
99 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
102 * Local Bus Definitions
105 /* Set the local bus clock 1/8 of platform clock */
106 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
108 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
109 #ifdef CONFIG_PHYS_64BIT
110 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
112 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
115 #define CONFIG_SYS_FLASH_BR_PRELIM \
116 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
118 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
119 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
121 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
122 #ifdef CONFIG_PHYS_64BIT
123 #define PIXIS_BASE_PHYS 0xfffdf0000ull
125 #define PIXIS_BASE_PHYS PIXIS_BASE
128 #define PIXIS_LBMAP_SWITCH 7
129 #define PIXIS_LBMAP_MASK 0xf0
130 #define PIXIS_LBMAP_SHIFT 4
131 #define PIXIS_LBMAP_ALTBANK 0x40
133 #define CONFIG_SYS_FLASH_QUIET_TEST
134 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
136 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
137 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
138 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
140 #if defined(CONFIG_RAMBOOT_PBL)
141 #define CONFIG_SYS_RAMBOOT
145 #ifdef CONFIG_NAND_FSL_ELBC
146 #define CONFIG_SYS_NAND_BASE 0xffa00000
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
150 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
153 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
154 #define CONFIG_SYS_MAX_NAND_DEVICE 1
156 /* NAND flash config */
157 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
158 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
159 | BR_PS_8 /* Port Size = 8 bit */ \
160 | BR_MS_FCM /* MSEL = FCM */ \
162 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
163 | OR_FCM_PGS /* Large Page*/ \
170 #endif /* CONFIG_NAND_FSL_ELBC */
172 #define CONFIG_SYS_FLASH_EMPTY_INFO
173 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
175 #define CONFIG_HWCONFIG
177 /* define to use L1 as initial stack */
178 #define CONFIG_L1_INIT_RAM
179 #define CONFIG_SYS_INIT_RAM_LOCK
180 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
181 #ifdef CONFIG_PHYS_64BIT
182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
184 /* The assembler doesn't like typecast */
185 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
186 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
187 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
189 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
190 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
193 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
195 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
197 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
199 /* Serial Port - controlled on board with jumper J8
203 #define CONFIG_SYS_NS16550_SERIAL
204 #define CONFIG_SYS_NS16550_REG_SIZE 1
205 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
207 #define CONFIG_SYS_BAUDRATE_TABLE \
208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
210 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
211 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
212 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
213 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
220 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
221 #ifdef CONFIG_PHYS_64BIT
222 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
224 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
226 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
228 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
229 #ifdef CONFIG_PHYS_64BIT
230 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
232 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
234 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
237 * for slave u-boot IMAGE instored in master memory space,
238 * PHYS must be aligned based on the SIZE
240 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
241 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
242 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
243 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
245 * for slave UCODE and ENV instored in master memory space,
246 * PHYS must be aligned based on the SIZE
248 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
249 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
250 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
252 /* slave core release by master*/
253 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
254 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
257 * SRIO_PCIE_BOOT - SLAVE
259 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
260 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
261 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
262 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
266 * eSPI - Enhanced SPI
271 * Memory space is mapped 1-1, but I/O space must start from 0.
274 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
275 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
276 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
277 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
278 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
280 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
281 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
282 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
283 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
284 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
286 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
287 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
288 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
289 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
290 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
292 /* controller 4, Base address 203000 */
293 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
294 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
297 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
298 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
299 #ifdef CONFIG_PHYS_64BIT
300 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
302 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
304 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
305 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
306 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
307 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
308 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
309 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
310 CONFIG_SYS_BMAN_CENA_SIZE)
311 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
312 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
313 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
314 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
315 #ifdef CONFIG_PHYS_64BIT
316 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
318 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
320 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
321 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
322 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
323 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
324 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
325 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
326 CONFIG_SYS_QMAN_CENA_SIZE)
327 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
328 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
330 #define CONFIG_SYS_DPAA_FMAN
331 #define CONFIG_SYS_DPAA_PME
332 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
335 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
336 #endif /* CONFIG_PCI */
338 #ifdef CONFIG_FMAN_ENET
339 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
340 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
341 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
342 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
343 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
345 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
346 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
347 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
348 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
349 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
351 #define CONFIG_SYS_TBIPA_VALUE 8
357 #define CONFIG_LOADS_ECHO /* echo on for serial download */
358 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
361 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
362 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
366 * Miscellaneous configurable options
370 * For booting Linux, the board info and command line data
371 * have to be in the first 64 MB of memory, since this is
372 * the maximum mapped by the Linux kernel during initialization.
374 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
375 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
378 * Environment Configuration
380 #define CONFIG_ROOTPATH "/opt/nfsroot"
381 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
383 #ifdef CONFIG_TARGET_P4080DS
384 #define __USB_PHY_TYPE ulpi
386 #define __USB_PHY_TYPE utmi
389 #define CONFIG_EXTRA_ENV_SETTINGS \
390 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
391 "bank_intlv=cs0_cs1;" \
392 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
393 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
395 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
396 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
397 "tftpflash=tftpboot $loadaddr $uboot && " \
398 "protect off $ubootaddr +$filesize && " \
399 "erase $ubootaddr +$filesize && " \
400 "cp.b $loadaddr $ubootaddr $filesize && " \
401 "protect on $ubootaddr +$filesize && " \
402 "cmp.b $loadaddr $ubootaddr $filesize\0" \
403 "consoledev=ttyS0\0" \
404 "ramdiskaddr=2000000\0" \
405 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
406 "fdtaddr=1e00000\0" \
407 "fdtfile=p4080ds/p4080ds.dtb\0" \
410 #include <asm/fsl_secure_boot.h>
412 #endif /* __CONFIG_H */