include/configs/coreboot.h

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * (C) Copyright 2008
   4  * Graeme Russ, graeme.russ@gmail.com.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <asm/ibmpc.h>
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_SYS_COREBOOT
  38 #undef CONFIG_SHOW_BOOT_PROGRESS
  39 #define CONFIG_LAST_STAGE_INIT
  40 #define CONFIG_X86_NO_RESET_VECTOR
  41
  42 /*-----------------------------------------------------------------------
  43  * Watchdog Configuration
  44  */
  45 #undef CONFIG_WATCHDOG
  46 #undef CONFIG_HW_WATCHDOG
  47
  48 /* SATA AHCI storage */
  49
  50 #define CONFIG_SCSI_AHCI
  51
  52 #ifdef CONFIG_SCSI_AHCI
  53 #define CONFIG_SYS_64BIT_LBA
  54 #define CONFIG_SATA_INTEL               1
  55 #define CONFIG_SCSI_DEV_LIST            {PCI_VENDOR_ID_INTEL, \
  56                         PCI_DEVICE_ID_INTEL_NM10_AHCI},       \
  57         {PCI_VENDOR_ID_INTEL,           \
  58                         PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
  59         {PCI_VENDOR_ID_INTEL, \
  60                         PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
  61         {PCI_VENDOR_ID_INTEL,           \
  62                         PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
  63
  64 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     2
  65 #define CONFIG_SYS_SCSI_MAX_LUN         1
  66 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  67                                          CONFIG_SYS_SCSI_MAX_LUN)
  68 #endif
  69
  70 /* Generic TPM interfaced through LPC bus */
  71 #define CONFIG_GENERIC_LPC_TPM
  72 #define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
  73
  74 /*-----------------------------------------------------------------------
  75  * Real Time Clock Configuration
  76  */
  77 #define CONFIG_RTC_MC146818
  78 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS  0
  79
  80 /*-----------------------------------------------------------------------
  81  * Serial Configuration
  82  */
  83 #define CONFIG_CONS_INDEX               1
  84 #define CONFIG_SYS_NS16550
  85 #define CONFIG_SYS_NS16550_SERIAL
  86 #define CONFIG_SYS_NS16550_REG_SIZE     1
  87 #define CONFIG_SYS_NS16550_CLK          1843200
  88 #define CONFIG_BAUDRATE                 9600
  89 #define CONFIG_SYS_BAUDRATE_TABLE       {300, 600, 1200, 2400, 4800, \
  90                                          9600, 19200, 38400, 115200}
  91 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
  92 #define CONFIG_SYS_NS16550_COM2 UART1_BASE
  93 #define CONFIG_SYS_NS16550_PORT_MAPPED
  94
  95 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,eserial0\0" \
  96                                         "stdout=vga,eserial0,cbmem\0" \
  97                                         "stderr=vga,eserial0,cbmem\0"
  98
  99 #define CONFIG_CONSOLE_MUX
 100 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 101 #define CONFIG_SYS_STDIO_DEREGISTER
 102 #define CONFIG_CBMEM_CONSOLE
 103
 104 /* max. 1 IDE bus       */
 105 #define CONFIG_SYS_IDE_MAXBUS           1
 106 /* max. 1 drive per IDE bus */
 107 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS * 1)
 108
 109 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_ISA_IO_BASE_ADDRESS
 110 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01f0
 111 #define CONFIG_SYS_ATA_IDE1_OFFSET      0x0170
 112 #define CONFIG_SYS_ATA_DATA_OFFSET      0
 113 #define CONFIG_SYS_ATA_REG_OFFSET       0
 114 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200
 115
 116
 117 #define CONFIG_SUPPORT_VFAT
 118 /************************************************************
 119  * ATAPI support (experimental)
 120  ************************************************************/
 121 #define CONFIG_ATAPI
 122
 123 /************************************************************
 124  * DISK Partition support
 125  ************************************************************/
 126 #define CONFIG_DOS_PARTITION
 127 #define CONFIG_MAC_PARTITION
 128 #define CONFIG_ISO_PARTITION            /* Experimental */
 129
 130 #define CONFIG_CMD_CBFS
 131 #define CONFIG_CMD_EXT4
 132 #define CONFIG_CMD_EXT4_WRITE
 133
 134 /*-----------------------------------------------------------------------
 135  * Video Configuration
 136  */
 137 #undef CONFIG_VIDEO
 138 #undef CONFIG_CFB_CONSOLE
 139
 140 /*-----------------------------------------------------------------------
 141  * Command line configuration.
 142  */
 143 #include <config_cmd_default.h>
 144
 145 #define CONFIG_CMD_BDI
 146 #define CONFIG_CMD_BOOTD
 147 #define CONFIG_CMD_CONSOLE
 148 #define CONFIG_CMD_DATE
 149 #define CONFIG_CMD_ECHO
 150 #undef CONFIG_CMD_FLASH
 151 #define CONFIG_CMD_FPGA
 152 #define CONFIG_CMD_IMI
 153 #undef CONFIG_CMD_IMLS
 154 #define CONFIG_CMD_IRQ
 155 #define CONFIG_CMD_ITEST
 156 #define CONFIG_CMD_LOADB
 157 #define CONFIG_CMD_LOADS
 158 #define CONFIG_CMD_MEMORY
 159 #define CONFIG_CMD_MISC
 160 #define CONFIG_CMD_NET
 161 #undef CONFIG_CMD_NFS
 162 #define CONFIG_CMD_PCI
 163 #define CONFIG_CMD_PING
 164 #define CONFIG_CMD_RUN
 165 #define CONFIG_CMD_SAVEENV
 166 #define CONFIG_CMD_SETGETDCR
 167 #define CONFIG_CMD_SOURCE
 168 #define CONFIG_CMD_XIMG
 169 #define CONFIG_CMD_IDE
 170 #define CONFIG_CMD_FAT
 171 #define CONFIG_CMD_EXT2
 172
 173 #define CONFIG_BOOTDELAY        2
 174 #define CONFIG_BOOTARGS         "root=/dev/mtdblock0 console=ttyS0,9600"
 175
 176 #if defined(CONFIG_CMD_KGDB)
 177 #define CONFIG_KGDB_BAUDRATE                    115200
 178 #define CONFIG_KGDB_SER_INDEX                   2
 179 #endif
 180
 181 /*
 182  * Miscellaneous configurable options
 183  */
 184 #define CONFIG_SYS_LONGHELP
 185 #define CONFIG_SYS_PROMPT                       "boot > "
 186 #define CONFIG_SYS_CBSIZE                       256
 187 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE + \
 188                                                  sizeof(CONFIG_SYS_PROMPT) + \
 189                                                  16)
 190 #define CONFIG_SYS_MAXARGS                      16
 191 #define CONFIG_SYS_BARGSIZE                     CONFIG_SYS_CBSIZE
 192
 193 #define CONFIG_SYS_MEMTEST_START                0x00100000
 194 #define CONFIG_SYS_MEMTEST_END                  0x01000000
 195 #define CONFIG_SYS_LOAD_ADDR                    0x100000
 196 #define CONFIG_SYS_HZ                           1000
 197 #define CONFIG_SYS_X86_ISR_TIMER
 198
 199 /*-----------------------------------------------------------------------
 200  * SDRAM Configuration
 201  */
 202 #define CONFIG_NR_DRAM_BANKS                    4
 203
 204 /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
 205 #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
 206 #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
 207 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
 208 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
 209
 210 /*-----------------------------------------------------------------------
 211  * CPU Features
 212  */
 213
 214 #define CONFIG_SYS_GENERIC_TIMER
 215 #define CONFIG_SYS_PCAT_INTERRUPTS
 216 #define CONFIG_SYS_NUM_IRQS                     16
 217
 218 /*-----------------------------------------------------------------------
 219  * Memory organization:
 220  * 32kB Stack
 221  * 16kB Cache-As-RAM @ 0x19200000
 222  * 256kB Monitor
 223  * (128kB + Environment Sector Size) malloc pool
 224  */
 225 #define CONFIG_SYS_STACK_SIZE                   (32 * 1024)
 226 #define CONFIG_SYS_CAR_ADDR                     0x19200000
 227 #define CONFIG_SYS_CAR_SIZE                     (16 * 1024)
 228 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 229 #define CONFIG_SYS_MONITOR_LEN                  (256 * 1024)
 230 #define CONFIG_SYS_MALLOC_LEN                   (0x20000 + 128 * 1024)
 231
 232
 233 /* allow to overwrite serial and ethaddr */
 234 #define CONFIG_ENV_OVERWRITE
 235
 236 /*-----------------------------------------------------------------------
 237  * FLASH configuration
 238  */
 239 #define CONFIG_SYS_NO_FLASH
 240 #undef CONFIG_FLASH_CFI_DRIVER
 241 #define CONFIG_SYS_MAX_FLASH_SECT               1
 242 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 243
 244 /*-----------------------------------------------------------------------
 245  * Environment configuration
 246  */
 247 #define CONFIG_ENV_IS_NOWHERE
 248 #define CONFIG_ENV_SIZE                 0x01000
 249
 250 /*-----------------------------------------------------------------------
 251  * PCI configuration
 252  */
 253 #define CONFIG_PCI
 254
 255 #define CONFIG_EXTRA_ENV_SETTINGS \
 256         CONFIG_STD_DEVICES_SETTINGS
 257
 258 #endif  /* __CONFIG_H */