1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
7 #ifndef _CONFIG_CONTROLCENTERDC_H
8 #define _CONFIG_CONTROLCENTERDC_H
11 * High Level Configuration Options (easy to change)
13 #define CONFIG_CUSTOMER_BOARD_SUPPORT
15 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
16 #define CONFIG_BOARD_LATE_INIT
19 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
20 * for DDR ECC byte filling in the SPL before loading the main
24 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
26 #define CONFIG_LOADADDR 1000000
29 * SDIO/MMC Card Configuration
31 #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
34 * SATA/SCSI/AHCI configuration
36 #define CONFIG_SCSI_AHCI_PLAT
37 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
38 #define CONFIG_SYS_SCSI_MAX_LUN 1
39 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
40 CONFIG_SYS_SCSI_MAX_LUN)
42 /* USB/EHCI configuration */
43 #define CONFIG_EHCI_IS_TDI
45 /* Environment in SPI NOR flash */
46 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
47 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
48 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
50 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
53 #ifndef CONFIG_SPL_BUILD
54 #define CONFIG_PCI_SCAN_SHOW
58 * Software (bit-bang) MII driver configuration
60 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
61 #define CONFIG_BITBANGMII_MULTI
65 * Select the boot device here
67 * Currently supported are:
68 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
69 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
71 #define SPL_BOOT_SPI_NOR_FLASH 1
72 #define SPL_BOOT_SDIO_MMC_CARD 2
73 #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
76 #define CONFIG_SPL_SIZE (160 << 10)
78 #if defined(CONFIG_SECURED_MODE_IMAGE)
79 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614)
81 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30)
84 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
85 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
87 #ifdef CONFIG_SPL_BUILD
88 #define CONFIG_SYS_MALLOC_SIMPLE
91 #define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10))
92 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
94 #define CONFIG_SPL_LIBCOMMON_SUPPORT
95 #define CONFIG_SPL_LIBGENERIC_SUPPORT
96 #define CONFIG_SPL_I2C_SUPPORT
98 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
99 /* SPL related SPI defines */
100 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x30000
101 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
104 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
105 /* SPL related MMC defines */
106 #define CONFIG_SPL_MMC_SUPPORT
107 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
108 #define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10)
109 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
110 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512)
111 #ifdef CONFIG_SPL_BUILD
112 #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
117 * Environment Configuration
119 #define CONFIG_ENV_OVERWRITE
121 #define CONFIG_BAUDRATE 115200
123 #define CONFIG_HOSTNAME "ccdc"
124 #define CONFIG_ROOTPATH "/opt/nfsroot"
125 #define CONFIG_BOOTFILE "ccdc.img"
127 #define CONFIG_PREBOOT /* enable preboot variable */
129 #define CONFIG_EXTRA_ENV_SETTINGS \
131 "consoledev=ttyS1\0" \
132 "u-boot=u-boot.bin\0" \
133 "bootfile_addr=1000000\0" \
134 "keyprogram_addr=3000000\0" \
135 "keyprogram_file=keyprogram.img\0" \
136 "fdtfile=controlcenterdc.dtb\0" \
137 "load=tftpboot ${loadaddr} ${u-boot}\0" \
139 "update=sf probe 1:0;" \
140 " sf erase 0 +${filesize};" \
141 " sf write ${fileaddr} 0 ${filesize}\0" \
142 "upd=run load update\0" \
143 "fdt_high=0x10000000\0" \
144 "initrd_high=0x10000000\0" \
145 "loadkeyprogram=tpm flush_keys;" \
147 " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\
148 " source ${keyprogram_addr}:script@1\0" \
149 "gpio1=gpio@22_25\0" \
151 "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \
152 "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \
153 "bootfail=for i in ${blinkseq}; do" \
154 " if test $i -eq 0; then" \
155 " gpio clear ${gpio1}; gpio set ${gpio2};" \
156 " elif test $i -eq 1; then" \
157 " gpio clear ${gpio1}; gpio clear ${gpio2};" \
158 " elif test $i -eq 2; then" \
159 " gpio set ${gpio1}; gpio set ${gpio2};" \
161 " gpio clear ${gpio1}; gpio set ${gpio2};" \
162 " fi; sleep 0.12; done\0"
164 #define CONFIG_NFSBOOTCOMMAND \
165 "setenv bootargs root=/dev/nfs rw " \
166 "nfsroot=${serverip}:${rootpath} " \
167 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \
168 "console=${consoledev},${baudrate} ${othbootargs}; " \
169 "tftpboot ${bootfile_addr} ${bootfile}; " \
170 "bootm ${bootfile_addr}"
172 #define CONFIG_MMCBOOTCOMMAND \
173 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
174 "console=${consoledev},${baudrate} ${othbootargs}; " \
175 "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \
176 "bootm ${bootfile_addr}"
178 #define CONFIG_BOOTCOMMAND \
179 "if env exists keyprogram; then;" \
180 " setenv keyprogram; run nfsboot;" \
185 * mv-common.h should be defined after CMD configs since it used them
186 * to enable certain macros
188 #include "mv-common.h"
190 #endif /* _CONFIG_CONTROLCENTERDC_H */