include/configs/controlcenterd.h

   1 /*
   2  * (C) Copyright 2013
   3  * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   4  *
   5  * based on P1022DS.h
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #ifdef CONFIG_SDCARD
  30 #define CONFIG_RAMBOOT_SDCARD
  31 #endif
  32
  33 #ifdef CONFIG_SPIFLASH
  34 #define CONFIG_RAMBOOT_SPIFLASH
  35 #endif
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_CONTROLCENTERD
  39 #define CONFIG_MP                       /* support multiple processors */
  40
  41 #define CONFIG_SYS_NO_FLASH
  42 #define CONFIG_ENABLE_36BIT_PHYS
  43
  44 #ifdef CONFIG_PHYS_64BIT
  45 #define CONFIG_ADDR_MAP
  46 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  47 #endif
  48
  49 #define CONFIG_L2_CACHE
  50 #define CONFIG_BTB
  51
  52 #define CONFIG_SYS_CLK_FREQ     66666600
  53 #define CONFIG_DDR_CLK_FREQ     66666600
  54
  55 #define CONFIG_SYS_RAMBOOT
  56
  57 #ifdef CONFIG_TRAILBLAZER
  58
  59 #define CONFIG_SYS_TEXT_BASE            0xf8fc0000
  60 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  61 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
  62
  63 /*
  64  * Config the L2 Cache
  65  */
  66 #define CONFIG_SYS_INIT_L2_ADDR         0xf8fc0000
  67 #ifdef CONFIG_PHYS_64BIT
  68 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8fc0000ull
  69 #else
  70 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
  71 #endif
  72 #define CONFIG_SYS_L2_SIZE              (256 << 10)
  73 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  74
  75 #else /* CONFIG_TRAILBLAZER */
  76
  77 #define CONFIG_SYS_TEXT_BASE            0x11000000
  78 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  79 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  80
  81 #endif /* CONFIG_TRAILBLAZER */
  82
  83 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  84 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
  85
  86 /*
  87  * Memory map
  88  *
  89  * 0x0000_0000  0x3fff_ffff     DDR                     1G Cacheable
  90  * 0xc000_0000  0xdfff_ffff     PCI Express Mem         512M non-cacheable
  91  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
  92  *
  93  * Localbus non-cacheable
  94  * 0xe000_0000  0xe00f_ffff     eLBC                    1M non-cacheable
  95  * 0xf8fc0000   0xf8ff_ffff     L2 SRAM                 256k Cacheable
  96  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
  97  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
  98  */
  99
 100 #define CONFIG_SYS_INIT_RAM_LOCK
 101 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 102 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* used area in RAM */
 103 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 104         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 105 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 106
 107 #ifdef CONFIG_TRAILBLAZER
 108 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
 109 #define CONFIG_SYS_CCSRBAR              CONFIG_SYS_CCSRBAR_DEFAULT
 110 #else
 111 #define CONFIG_SYS_CCSRBAR              0xffe00000
 112 #endif
 113 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 114 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR   (CONFIG_SYS_CCSRBAR+0xf200)
 115
 116 /*
 117  * DDR Setup
 118  */
 119
 120 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 121 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 122 #define CONFIG_SYS_SDRAM_SIZE 1024
 123 #define CONFIG_VERY_BIG_RAM
 124
 125 #define CONFIG_SYS_FSL_DDR3
 126 #define CONFIG_NUM_DDR_CONTROLLERS      1
 127 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 128 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 129
 130 #define CONFIG_SYS_MEMTEST_START        0x00000000
 131 #define CONFIG_SYS_MEMTEST_END          0x3fffffff
 132
 133 #ifdef CONFIG_TRAILBLAZER
 134 #define CONFIG_SPD_EEPROM
 135 #define SPD_EEPROM_ADDRESS 0x52
 136 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
 137 #endif
 138
 139 /*
 140  * Local Bus Definitions
 141  */
 142 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
 143
 144 #define CONFIG_SYS_ELBC_BASE            0xe0000000
 145 #ifdef CONFIG_PHYS_64BIT
 146 #define CONFIG_SYS_ELBC_BASE_PHYS       0xfe0000000ull
 147 #else
 148 #define CONFIG_SYS_ELBC_BASE_PHYS       CONFIG_SYS_ELBC_BASE
 149 #endif
 150
 151 #define CONFIG_UART_BR_PRELIM  \
 152         (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
 153 #define CONFIG_UART_OR_PRELIM   (OR_AM_32KB | 0xff7)
 154
 155 #define CONFIG_SYS_BR0_PRELIM   0 /* CS0 was originally intended for FPGA */
 156 #define CONFIG_SYS_OR0_PRELIM   0 /* debugging, was never used */
 157
 158 #define CONFIG_SYS_BR1_PRELIM   CONFIG_UART_BR_PRELIM
 159 #define CONFIG_SYS_OR1_PRELIM   CONFIG_UART_OR_PRELIM
 160
 161 /*
 162  * Serial Port
 163  */
 164 #define CONFIG_CONS_INDEX               2
 165 #define CONFIG_SYS_NS16550_SERIAL
 166 #define CONFIG_SYS_NS16550_REG_SIZE     1
 167 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 168
 169 #define CONFIG_SYS_BAUDRATE_TABLE       \
 170         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 171
 172 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 173 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 174
 175 /*
 176  * I2C
 177  */
 178 #define CONFIG_SYS_I2C
 179 #define CONFIG_SYS_I2C_FSL
 180 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 181 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 182 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 183 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 184 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 185 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 186
 187 #ifndef CONFIG_TRAILBLAZER
 188 #endif
 189
 190 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 191
 192 #define CONFIG_CMD_EEPROM
 193 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
 194 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 195
 196 #ifndef CONFIG_TRAILBLAZER
 197 /*
 198  * eSPI - Enhanced SPI
 199  */
 200 #define CONFIG_HARD_SPI
 201
 202 #define CONFIG_SF_DEFAULT_SPEED         10000000
 203 #define CONFIG_SF_DEFAULT_MODE          0
 204 #endif
 205
 206 #define CONFIG_SHA1
 207
 208 /*
 209  * MMC
 210  */
 211 #define CONFIG_GENERIC_MMC
 212
 213 #define CONFIG_FSL_ESDHC
 214 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 215
 216 #ifndef CONFIG_TRAILBLAZER
 217
 218 /*
 219  * Video
 220  */
 221 #define CONFIG_FSL_DIU_FB
 222 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 223 #define CONFIG_CMD_BMP
 224
 225 /*
 226  * General PCI
 227  * Memory space is mapped 1-1, but I/O space must start from 0.
 228  */
 229 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 230 #define CONFIG_PCI_INDIRECT_BRIDGE
 231 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 232 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 233 #define CONFIG_CMD_PCI
 234
 235 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 236 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 237
 238 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 239 #ifdef CONFIG_PHYS_64BIT
 240 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 241 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 242 #else
 243 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 244 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 245 #endif
 246 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 247 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 248 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 249 #ifdef CONFIG_PHYS_64BIT
 250 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 251 #else
 252 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 253 #endif
 254 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 255
 256 /*
 257  * SATA
 258  */
 259 #define CONFIG_LIBATA
 260 #define CONFIG_LBA48
 261 #define CONFIG_CMD_SATA
 262
 263 #define CONFIG_FSL_SATA
 264 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 265 #define CONFIG_SATA1
 266 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 267 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 268 #define CONFIG_SATA2
 269 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 270 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 271
 272 /*
 273  * Ethernet
 274  */
 275 #define CONFIG_TSEC_ENET
 276
 277 #define CONFIG_TSECV2
 278
 279 #define CONFIG_MII                      /* MII PHY management */
 280 #define CONFIG_TSEC1            1
 281 #define CONFIG_TSEC1_NAME       "eTSEC1"
 282 #define CONFIG_TSEC2            1
 283 #define CONFIG_TSEC2_NAME       "eTSEC2"
 284
 285 #define TSEC1_PHY_ADDR          0
 286 #define TSEC2_PHY_ADDR          1
 287
 288 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 289 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 290
 291 #define TSEC1_PHYIDX            0
 292 #define TSEC2_PHYIDX            0
 293
 294 #define CONFIG_ETHPRIME         "eTSEC1"
 295
 296 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 297
 298 /*
 299  * USB
 300  */
 301 #define CONFIG_USB_EHCI
 302
 303 #define CONFIG_HAS_FSL_DR_USB
 304 #define CONFIG_USB_EHCI_FSL
 305 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 306
 307 #endif /* CONFIG_TRAILBLAZER */
 308
 309 /*
 310  * Environment
 311  */
 312 #if defined(CONFIG_TRAILBLAZER)
 313 #define CONFIG_ENV_IS_NOWHERE
 314 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 315 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 316 #define CONFIG_ENV_IS_IN_SPI_FLASH
 317 #define CONFIG_ENV_SPI_BUS      0
 318 #define CONFIG_ENV_SPI_CS       0
 319 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 320 #define CONFIG_ENV_SPI_MODE     0
 321 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 322 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 323 #define CONFIG_ENV_SECT_SIZE    0x10000
 324 #elif defined(CONFIG_RAMBOOT_SDCARD)
 325 #define CONFIG_ENV_IS_IN_MMC
 326 #define CONFIG_FSL_FIXED_MMC_LOCATION
 327 #define CONFIG_ENV_SIZE         0x2000
 328 #define CONFIG_SYS_MMC_ENV_DEV  0
 329 #endif
 330
 331 #define CONFIG_SYS_EXTRA_ENV_RELOC
 332
 333 /*
 334  * Command line configuration.
 335  */
 336 #ifndef CONFIG_TRAILBLAZER
 337 #define CONFIG_SYS_LONGHELP
 338 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 339 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 340 #endif /* CONFIG_TRAILBLAZER */
 341
 342 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 343 #ifdef CONFIG_CMD_KGDB
 344 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 345 #else
 346 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 347 #endif
 348 /* Print Buffer Size */
 349 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 350 #define CONFIG_SYS_MAXARGS      16
 351 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 352
 353 #ifndef CONFIG_TRAILBLAZER
 354
 355 #define CONFIG_CMD_ERRATA
 356 #define CONFIG_CMD_IRQ
 357 #define CONFIG_CMD_REGINFO
 358
 359 /*
 360  * Board initialisation callbacks
 361  */
 362 #define CONFIG_BOARD_EARLY_INIT_F
 363 #define CONFIG_BOARD_EARLY_INIT_R
 364 #define CONFIG_MISC_INIT_R
 365 #define CONFIG_LAST_STAGE_INIT
 366
 367 #else /* CONFIG_TRAILBLAZER */
 368
 369 #define CONFIG_BOARD_EARLY_INIT_F
 370 #define CONFIG_BOARD_EARLY_INIT_R
 371 #define CONFIG_LAST_STAGE_INIT
 372
 373 #endif /* CONFIG_TRAILBLAZER */
 374
 375 /*
 376  * Miscellaneous configurable options
 377  */
 378 #define CONFIG_HW_WATCHDOG
 379 #define CONFIG_LOADS_ECHO
 380 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 381 #define CONFIG_DOS_PARTITION
 382
 383 /*
 384  * For booting Linux, the board info and command line data
 385  * have to be in the first 64 MB of memory, since this is
 386  * the maximum mapped by the Linux kernel during initialization.
 387  */
 388 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Linux Memory map */
 389 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 390
 391 /*
 392  * Environment Configuration
 393  */
 394
 395 #ifdef CONFIG_TRAILBLAZER
 396
 397 #define CONFIG_BAUDRATE 115200
 398
 399 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 400         "mp_holdoff=1\0"
 401
 402 #else
 403
 404 #define CONFIG_HOSTNAME         controlcenterd
 405 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 406 #define CONFIG_BOOTFILE         "uImage"
 407 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP */
 408
 409 #define CONFIG_LOADADDR         1000000
 410
 411
 412 #define CONFIG_BAUDRATE 115200
 413
 414 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 415         "netdev=eth0\0"                                         \
 416         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 417         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 418         "tftpflash=tftpboot $loadaddr $uboot && "               \
 419                 "protect off $ubootaddr +$filesize && "         \
 420                 "erase $ubootaddr +$filesize && "               \
 421                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 422                 "protect on $ubootaddr +$filesize && "          \
 423                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 424         "consoledev=ttyS1\0"                                    \
 425         "ramdiskaddr=2000000\0"                                 \
 426         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 427         "fdtaddr=1e00000\0"                                     \
 428         "fdtfile=controlcenterd.dtb\0"                          \
 429         "bdev=sda3\0"
 430
 431 /* these are used and NUL-terminated in env_default.h */
 432 #define CONFIG_NFSBOOTCOMMAND                                           \
 433         "setenv bootargs root=/dev/nfs rw "                             \
 434         "nfsroot=$serverip:$rootpath "                                  \
 435         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 436         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 437         "tftp $loadaddr $bootfile;"                                     \
 438         "tftp $fdtaddr $fdtfile;"                                       \
 439         "bootm $loadaddr - $fdtaddr"
 440
 441 #define CONFIG_RAMBOOTCOMMAND                                           \
 442         "setenv bootargs root=/dev/ram rw "                             \
 443         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 444         "tftp $ramdiskaddr $ramdiskfile;"                               \
 445         "tftp $loadaddr $bootfile;"                                     \
 446         "tftp $fdtaddr $fdtfile;"                                       \
 447         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 448
 449 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 450
 451 #endif /* CONFIG_TRAILBLAZER */
 452
 453 #endif