3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #define CONFIG_RAMBOOT_SDCARD
33 #ifdef CONFIG_SPIFLASH
34 #define CONFIG_RAMBOOT_SPIFLASH
37 /* High Level Configuration Options */
38 #define CONFIG_CONTROLCENTERD
39 #define CONFIG_MP /* support multiple processors */
41 #define CONFIG_SYS_NO_FLASH
42 #define CONFIG_ENABLE_36BIT_PHYS
44 #ifdef CONFIG_PHYS_64BIT
45 #define CONFIG_ADDR_MAP
46 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
49 #define CONFIG_L2_CACHE
52 #define CONFIG_SYS_CLK_FREQ 66666600
53 #define CONFIG_DDR_CLK_FREQ 66666600
55 #define CONFIG_SYS_RAMBOOT
57 #ifdef CONFIG_TRAILBLAZER
59 #define CONFIG_SYS_TEXT_BASE 0xf8fc0000
60 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
61 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
66 #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
67 #ifdef CONFIG_PHYS_64BIT
68 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
70 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
72 #define CONFIG_SYS_L2_SIZE (256 << 10)
73 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
75 #else /* CONFIG_TRAILBLAZER */
77 #define CONFIG_SYS_TEXT_BASE 0x11000000
78 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
79 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
81 #endif /* CONFIG_TRAILBLAZER */
83 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
84 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
89 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
90 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
91 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
93 * Localbus non-cacheable
94 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
95 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
96 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
97 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
100 #define CONFIG_SYS_INIT_RAM_LOCK
101 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
102 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
103 #define CONFIG_SYS_GBL_DATA_OFFSET \
104 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
105 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
107 #ifdef CONFIG_TRAILBLAZER
108 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
109 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
111 #define CONFIG_SYS_CCSRBAR 0xffe00000
113 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
114 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
120 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
122 #define CONFIG_SYS_SDRAM_SIZE 1024
123 #define CONFIG_VERY_BIG_RAM
125 #define CONFIG_NUM_DDR_CONTROLLERS 1
126 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
127 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
129 #define CONFIG_SYS_MEMTEST_START 0x00000000
130 #define CONFIG_SYS_MEMTEST_END 0x3fffffff
132 #ifdef CONFIG_TRAILBLAZER
133 #define CONFIG_SPD_EEPROM
134 #define SPD_EEPROM_ADDRESS 0x52
135 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
139 * Local Bus Definitions
141 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
143 #define CONFIG_SYS_ELBC_BASE 0xe0000000
144 #ifdef CONFIG_PHYS_64BIT
145 #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
147 #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
150 #define CONFIG_UART_BR_PRELIM \
151 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
152 #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
154 #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
155 #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
157 #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
158 #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
163 #define CONFIG_CONS_INDEX 2
164 #define CONFIG_SYS_NS16550_SERIAL
165 #define CONFIG_SYS_NS16550_REG_SIZE 1
166 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
168 #define CONFIG_SYS_BAUDRATE_TABLE \
169 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
171 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
172 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
177 #define CONFIG_SYS_I2C
178 #define CONFIG_SYS_I2C_FSL
179 #define CONFIG_SYS_FSL_I2C_SPEED 400000
180 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
181 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
182 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
183 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
184 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
186 #ifndef CONFIG_TRAILBLAZER
189 #define CONFIG_PCA9698 /* NXP PCA9698 */
191 #define CONFIG_CMD_EEPROM
192 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
193 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
195 #ifndef CONFIG_TRAILBLAZER
197 * eSPI - Enhanced SPI
199 #define CONFIG_HARD_SPI
201 #define CONFIG_SF_DEFAULT_SPEED 10000000
202 #define CONFIG_SF_DEFAULT_MODE 0
210 #define CONFIG_GENERIC_MMC
212 #define CONFIG_FSL_ESDHC
213 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
215 #ifndef CONFIG_TRAILBLAZER
220 #define CONFIG_FSL_DIU_FB
221 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
222 #define CONFIG_CMD_BMP
226 * Memory space is mapped 1-1, but I/O space must start from 0.
228 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
229 #define CONFIG_PCI_INDIRECT_BRIDGE
230 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
231 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
232 #define CONFIG_CMD_PCI
234 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
235 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
237 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
238 #ifdef CONFIG_PHYS_64BIT
239 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
240 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
242 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
243 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
245 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
246 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
247 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
248 #ifdef CONFIG_PHYS_64BIT
249 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
251 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
253 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
258 #define CONFIG_LIBATA
260 #define CONFIG_CMD_SATA
262 #define CONFIG_FSL_SATA
263 #define CONFIG_SYS_SATA_MAX_DEVICE 2
265 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
266 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
268 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
269 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
274 #define CONFIG_TSEC_ENET
276 #define CONFIG_TSECV2
278 #define CONFIG_MII /* MII PHY management */
279 #define CONFIG_TSEC1 1
280 #define CONFIG_TSEC1_NAME "eTSEC1"
281 #define CONFIG_TSEC2 1
282 #define CONFIG_TSEC2_NAME "eTSEC2"
284 #define TSEC1_PHY_ADDR 0
285 #define TSEC2_PHY_ADDR 1
287 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
288 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
290 #define TSEC1_PHYIDX 0
291 #define TSEC2_PHYIDX 0
293 #define CONFIG_ETHPRIME "eTSEC1"
295 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
300 #define CONFIG_USB_EHCI
302 #define CONFIG_HAS_FSL_DR_USB
303 #define CONFIG_USB_EHCI_FSL
304 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
306 #endif /* CONFIG_TRAILBLAZER */
311 #if defined(CONFIG_TRAILBLAZER)
312 #define CONFIG_ENV_IS_NOWHERE
313 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
314 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
315 #define CONFIG_ENV_IS_IN_SPI_FLASH
316 #define CONFIG_ENV_SPI_BUS 0
317 #define CONFIG_ENV_SPI_CS 0
318 #define CONFIG_ENV_SPI_MAX_HZ 10000000
319 #define CONFIG_ENV_SPI_MODE 0
320 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
321 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
322 #define CONFIG_ENV_SECT_SIZE 0x10000
323 #elif defined(CONFIG_RAMBOOT_SDCARD)
324 #define CONFIG_ENV_IS_IN_MMC
325 #define CONFIG_FSL_FIXED_MMC_LOCATION
326 #define CONFIG_ENV_SIZE 0x2000
327 #define CONFIG_SYS_MMC_ENV_DEV 0
330 #define CONFIG_SYS_EXTRA_ENV_RELOC
333 * Command line configuration.
335 #ifndef CONFIG_TRAILBLAZER
336 #define CONFIG_SYS_LONGHELP
337 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
338 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
339 #endif /* CONFIG_TRAILBLAZER */
341 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
342 #ifdef CONFIG_CMD_KGDB
343 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
345 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
347 /* Print Buffer Size */
348 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
349 #define CONFIG_SYS_MAXARGS 16
350 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
352 #ifndef CONFIG_TRAILBLAZER
354 #define CONFIG_CMD_ERRATA
355 #define CONFIG_CMD_IRQ
356 #define CONFIG_CMD_REGINFO
359 * Board initialisation callbacks
361 #define CONFIG_BOARD_EARLY_INIT_F
362 #define CONFIG_BOARD_EARLY_INIT_R
363 #define CONFIG_MISC_INIT_R
364 #define CONFIG_LAST_STAGE_INIT
366 #else /* CONFIG_TRAILBLAZER */
368 #define CONFIG_BOARD_EARLY_INIT_F
369 #define CONFIG_BOARD_EARLY_INIT_R
370 #define CONFIG_LAST_STAGE_INIT
372 #endif /* CONFIG_TRAILBLAZER */
375 * Miscellaneous configurable options
377 #define CONFIG_HW_WATCHDOG
378 #define CONFIG_LOADS_ECHO
379 #define CONFIG_SYS_LOADS_BAUD_CHANGE
380 #define CONFIG_DOS_PARTITION
383 * For booting Linux, the board info and command line data
384 * have to be in the first 64 MB of memory, since this is
385 * the maximum mapped by the Linux kernel during initialization.
387 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
388 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
391 * Environment Configuration
394 #ifdef CONFIG_TRAILBLAZER
396 #define CONFIG_BAUDRATE 115200
398 #define CONFIG_EXTRA_ENV_SETTINGS \
403 #define CONFIG_HOSTNAME controlcenterd
404 #define CONFIG_ROOTPATH "/opt/nfsroot"
405 #define CONFIG_BOOTFILE "uImage"
406 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
408 #define CONFIG_LOADADDR 1000000
411 #define CONFIG_BAUDRATE 115200
413 #define CONFIG_EXTRA_ENV_SETTINGS \
415 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
416 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
417 "tftpflash=tftpboot $loadaddr $uboot && " \
418 "protect off $ubootaddr +$filesize && " \
419 "erase $ubootaddr +$filesize && " \
420 "cp.b $loadaddr $ubootaddr $filesize && " \
421 "protect on $ubootaddr +$filesize && " \
422 "cmp.b $loadaddr $ubootaddr $filesize\0" \
423 "consoledev=ttyS1\0" \
424 "ramdiskaddr=2000000\0" \
425 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
426 "fdtaddr=1e00000\0" \
427 "fdtfile=controlcenterd.dtb\0" \
430 /* these are used and NUL-terminated in env_default.h */
431 #define CONFIG_NFSBOOTCOMMAND \
432 "setenv bootargs root=/dev/nfs rw " \
433 "nfsroot=$serverip:$rootpath " \
434 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
435 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
436 "tftp $loadaddr $bootfile;" \
437 "tftp $fdtaddr $fdtfile;" \
438 "bootm $loadaddr - $fdtaddr"
440 #define CONFIG_RAMBOOTCOMMAND \
441 "setenv bootargs root=/dev/ram rw " \
442 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
443 "tftp $ramdiskaddr $ramdiskfile;" \
444 "tftp $loadaddr $bootfile;" \
445 "tftp $fdtaddr $fdtfile;" \
446 "bootm $loadaddr $ramdiskaddr $fdtaddr"
448 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
450 #endif /* CONFIG_TRAILBLAZER */