include/configs/controlcenterd.h

   1 /*
   2  * (C) Copyright 2013
   3  * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   4  *
   5  * based on P1022DS.h
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #ifdef CONFIG_SDCARD
  30 #define CONFIG_RAMBOOT_SDCARD
  31 #endif
  32
  33 #ifdef CONFIG_SPIFLASH
  34 #define CONFIG_RAMBOOT_SPIFLASH
  35 #endif
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE                    /* BOOKE */
  39 #define CONFIG_E500                     /* BOOKE e500 family */
  40 #define CONFIG_CONTROLCENTERD
  41 #define CONFIG_MP                       /* support multiple processors */
  42
  43 #define CONFIG_SYS_NO_FLASH
  44 #define CONFIG_ENABLE_36BIT_PHYS
  45 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  46
  47 #ifdef CONFIG_PHYS_64BIT
  48 #define CONFIG_ADDR_MAP
  49 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
  50 #endif
  51
  52 #define CONFIG_L2_CACHE
  53 #define CONFIG_BTB
  54
  55 #define CONFIG_SYS_CLK_FREQ     66666600
  56 #define CONFIG_DDR_CLK_FREQ     66666600
  57
  58 #define CONFIG_SYS_RAMBOOT
  59
  60 #ifdef CONFIG_TRAILBLAZER
  61
  62 #define CONFIG_SYS_TEXT_BASE            0xf8fc0000
  63 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
  64 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
  65
  66 /*
  67  * Config the L2 Cache
  68  */
  69 #define CONFIG_SYS_INIT_L2_ADDR         0xf8fc0000
  70 #ifdef CONFIG_PHYS_64BIT
  71 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8fc0000ull
  72 #else
  73 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
  74 #endif
  75 #define CONFIG_SYS_L2_SIZE              (256 << 10)
  76 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  77
  78 #else /* CONFIG_TRAILBLAZER */
  79
  80 #define CONFIG_SYS_TEXT_BASE            0x11000000
  81 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  82 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
  83
  84 #endif /* CONFIG_TRAILBLAZER */
  85
  86 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
  87 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
  88
  89 /*
  90  * Memory map
  91  *
  92  * 0x0000_0000  0x3fff_ffff     DDR                     1G Cacheable
  93  * 0xc000_0000  0xdfff_ffff     PCI Express Mem         512M non-cacheable
  94  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
  95  *
  96  * Localbus non-cacheable
  97  * 0xe000_0000  0xe00f_ffff     eLBC                    1M non-cacheable
  98  * 0xf8fc0000   0xf8ff_ffff     L2 SRAM                 256k Cacheable
  99  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
 100  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
 101  */
 102
 103 #define CONFIG_SYS_INIT_RAM_LOCK
 104 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
 105 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* used area in RAM */
 106 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 107         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 108 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 109
 110 #ifdef CONFIG_TRAILBLAZER
 111 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
 112 #define CONFIG_SYS_CCSRBAR              CONFIG_SYS_CCSRBAR_DEFAULT
 113 #else
 114 #define CONFIG_SYS_CCSRBAR              0xffe00000
 115 #endif
 116 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 117 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR   (CONFIG_SYS_CCSRBAR+0xf200)
 118
 119 /*
 120  * DDR Setup
 121  */
 122
 123 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 124 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 125 #define CONFIG_SYS_SDRAM_SIZE 1024
 126 #define CONFIG_VERY_BIG_RAM
 127
 128 #define CONFIG_SYS_FSL_DDR3
 129 #define CONFIG_NUM_DDR_CONTROLLERS      1
 130 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 131 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 132
 133 #define CONFIG_SYS_MEMTEST_START        0x00000000
 134 #define CONFIG_SYS_MEMTEST_END          0x3fffffff
 135
 136 #ifdef CONFIG_TRAILBLAZER
 137 #define CONFIG_SPD_EEPROM
 138 #define SPD_EEPROM_ADDRESS 0x52
 139 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
 140 #endif
 141
 142 /*
 143  * Local Bus Definitions
 144  */
 145 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
 146
 147 #define CONFIG_SYS_ELBC_BASE            0xe0000000
 148 #ifdef CONFIG_PHYS_64BIT
 149 #define CONFIG_SYS_ELBC_BASE_PHYS       0xfe0000000ull
 150 #else
 151 #define CONFIG_SYS_ELBC_BASE_PHYS       CONFIG_SYS_ELBC_BASE
 152 #endif
 153
 154 #define CONFIG_UART_BR_PRELIM  \
 155         (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
 156 #define CONFIG_UART_OR_PRELIM   (OR_AM_32KB | 0xff7)
 157
 158 #define CONFIG_SYS_BR0_PRELIM   0 /* CS0 was originally intended for FPGA */
 159 #define CONFIG_SYS_OR0_PRELIM   0 /* debugging, was never used */
 160
 161 #define CONFIG_SYS_BR1_PRELIM   CONFIG_UART_BR_PRELIM
 162 #define CONFIG_SYS_OR1_PRELIM   CONFIG_UART_OR_PRELIM
 163
 164 /*
 165  * Serial Port
 166  */
 167 #define CONFIG_CONS_INDEX               2
 168 #define CONFIG_SYS_NS16550_SERIAL
 169 #define CONFIG_SYS_NS16550_REG_SIZE     1
 170 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 171
 172 #define CONFIG_SYS_BAUDRATE_TABLE       \
 173         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 174
 175 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 176 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 177
 178 /*
 179  * I2C
 180  */
 181 #define CONFIG_SYS_I2C
 182 #define CONFIG_SYS_I2C_FSL
 183 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 184 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 185 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 186 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 187 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 188 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 189
 190 #ifndef CONFIG_TRAILBLAZER
 191 #endif
 192
 193 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 194
 195 #define CONFIG_CMD_EEPROM
 196 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
 197 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 198
 199 #ifndef CONFIG_TRAILBLAZER
 200 /*
 201  * eSPI - Enhanced SPI
 202  */
 203 #define CONFIG_HARD_SPI
 204
 205 #define CONFIG_SF_DEFAULT_SPEED         10000000
 206 #define CONFIG_SF_DEFAULT_MODE          0
 207 #endif
 208
 209 #define CONFIG_SHA1
 210
 211 /*
 212  * MMC
 213  */
 214 #define CONFIG_MMC
 215 #define CONFIG_GENERIC_MMC
 216
 217 #define CONFIG_FSL_ESDHC
 218 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 219
 220 #ifndef CONFIG_TRAILBLAZER
 221
 222 /*
 223  * Video
 224  */
 225 #define CONFIG_FSL_DIU_FB
 226 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
 227 #define CONFIG_CMD_BMP
 228
 229 /*
 230  * General PCI
 231  * Memory space is mapped 1-1, but I/O space must start from 0.
 232  */
 233 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
 234 #define CONFIG_PCI_INDIRECT_BRIDGE
 235 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 236 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 237 #define CONFIG_CMD_PCI
 238
 239 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 240 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
 241
 242 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 243 #ifdef CONFIG_PHYS_64BIT
 244 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 245 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
 246 #else
 247 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
 248 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
 249 #endif
 250 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 251 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 252 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 253 #ifdef CONFIG_PHYS_64BIT
 254 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
 255 #else
 256 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
 257 #endif
 258 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 259
 260 /*
 261  * SATA
 262  */
 263 #define CONFIG_LIBATA
 264 #define CONFIG_LBA48
 265 #define CONFIG_CMD_SATA
 266
 267 #define CONFIG_FSL_SATA
 268 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 269 #define CONFIG_SATA1
 270 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 271 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 272 #define CONFIG_SATA2
 273 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 274 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 275
 276 /*
 277  * Ethernet
 278  */
 279 #define CONFIG_TSEC_ENET
 280
 281 #define CONFIG_TSECV2
 282
 283 #define CONFIG_MII                      /* MII PHY management */
 284 #define CONFIG_TSEC1            1
 285 #define CONFIG_TSEC1_NAME       "eTSEC1"
 286 #define CONFIG_TSEC2            1
 287 #define CONFIG_TSEC2_NAME       "eTSEC2"
 288
 289 #define TSEC1_PHY_ADDR          0
 290 #define TSEC2_PHY_ADDR          1
 291
 292 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 293 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 294
 295 #define TSEC1_PHYIDX            0
 296 #define TSEC2_PHYIDX            0
 297
 298 #define CONFIG_ETHPRIME         "eTSEC1"
 299
 300 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 301
 302 /*
 303  * USB
 304  */
 305 #define CONFIG_USB_EHCI
 306
 307 #define CONFIG_HAS_FSL_DR_USB
 308 #define CONFIG_USB_EHCI_FSL
 309 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 310
 311 #endif /* CONFIG_TRAILBLAZER */
 312
 313 /*
 314  * Environment
 315  */
 316 #if defined(CONFIG_TRAILBLAZER)
 317 #define CONFIG_ENV_IS_NOWHERE
 318 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 319 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 320 #define CONFIG_ENV_IS_IN_SPI_FLASH
 321 #define CONFIG_ENV_SPI_BUS      0
 322 #define CONFIG_ENV_SPI_CS       0
 323 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 324 #define CONFIG_ENV_SPI_MODE     0
 325 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
 326 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 327 #define CONFIG_ENV_SECT_SIZE    0x10000
 328 #elif defined(CONFIG_RAMBOOT_SDCARD)
 329 #define CONFIG_ENV_IS_IN_MMC
 330 #define CONFIG_FSL_FIXED_MMC_LOCATION
 331 #define CONFIG_ENV_SIZE         0x2000
 332 #define CONFIG_SYS_MMC_ENV_DEV  0
 333 #endif
 334
 335 #define CONFIG_SYS_EXTRA_ENV_RELOC
 336
 337 /*
 338  * Command line configuration.
 339  */
 340 #ifndef CONFIG_TRAILBLAZER
 341 #define CONFIG_SYS_LONGHELP
 342 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 343 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 344 #endif /* CONFIG_TRAILBLAZER */
 345
 346 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 347 #ifdef CONFIG_CMD_KGDB
 348 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 349 #else
 350 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 351 #endif
 352 /* Print Buffer Size */
 353 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 354 #define CONFIG_SYS_MAXARGS      16
 355 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 356
 357 #ifndef CONFIG_TRAILBLAZER
 358
 359 #define CONFIG_CMD_ERRATA
 360 #define CONFIG_CMD_IRQ
 361 #define CONFIG_CMD_REGINFO
 362
 363 /*
 364  * Board initialisation callbacks
 365  */
 366 #define CONFIG_BOARD_EARLY_INIT_F
 367 #define CONFIG_BOARD_EARLY_INIT_R
 368 #define CONFIG_MISC_INIT_R
 369 #define CONFIG_LAST_STAGE_INIT
 370
 371 #else /* CONFIG_TRAILBLAZER */
 372
 373 #define CONFIG_BOARD_EARLY_INIT_F
 374 #define CONFIG_BOARD_EARLY_INIT_R
 375 #define CONFIG_LAST_STAGE_INIT
 376
 377 #endif /* CONFIG_TRAILBLAZER */
 378
 379 /*
 380  * Miscellaneous configurable options
 381  */
 382 #define CONFIG_HW_WATCHDOG
 383 #define CONFIG_LOADS_ECHO
 384 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 385 #define CONFIG_DOS_PARTITION
 386
 387 /*
 388  * For booting Linux, the board info and command line data
 389  * have to be in the first 64 MB of memory, since this is
 390  * the maximum mapped by the Linux kernel during initialization.
 391  */
 392 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Linux Memory map */
 393 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 394
 395 /*
 396  * Environment Configuration
 397  */
 398
 399 #ifdef CONFIG_TRAILBLAZER
 400
 401 #define CONFIG_BAUDRATE 115200
 402
 403 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 404         "mp_holdoff=1\0"
 405
 406 #else
 407
 408 #define CONFIG_HOSTNAME         controlcenterd
 409 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 410 #define CONFIG_BOOTFILE         "uImage"
 411 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP */
 412
 413 #define CONFIG_LOADADDR         1000000
 414
 415
 416 #define CONFIG_BAUDRATE 115200
 417
 418 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 419         "netdev=eth0\0"                                         \
 420         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 421         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 422         "tftpflash=tftpboot $loadaddr $uboot && "               \
 423                 "protect off $ubootaddr +$filesize && "         \
 424                 "erase $ubootaddr +$filesize && "               \
 425                 "cp.b $loadaddr $ubootaddr $filesize && "       \
 426                 "protect on $ubootaddr +$filesize && "          \
 427                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
 428         "consoledev=ttyS1\0"                                    \
 429         "ramdiskaddr=2000000\0"                                 \
 430         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
 431         "fdtaddr=1e00000\0"                                     \
 432         "fdtfile=controlcenterd.dtb\0"                          \
 433         "bdev=sda3\0"
 434
 435 /* these are used and NUL-terminated in env_default.h */
 436 #define CONFIG_NFSBOOTCOMMAND                                           \
 437         "setenv bootargs root=/dev/nfs rw "                             \
 438         "nfsroot=$serverip:$rootpath "                                  \
 439         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 440         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 441         "tftp $loadaddr $bootfile;"                                     \
 442         "tftp $fdtaddr $fdtfile;"                                       \
 443         "bootm $loadaddr - $fdtaddr"
 444
 445 #define CONFIG_RAMBOOTCOMMAND                                           \
 446         "setenv bootargs root=/dev/ram rw "                             \
 447         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
 448         "tftp $ramdiskaddr $ramdiskfile;"                               \
 449         "tftp $loadaddr $bootfile;"                                     \
 450         "tftp $fdtaddr $fdtfile;"                                       \
 451         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 452
 453 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
 454
 455 #endif /* CONFIG_TRAILBLAZER */
 456
 457 #endif