3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #define CONFIG_RAMBOOT_SDCARD
33 #ifdef CONFIG_SPIFLASH
34 #define CONFIG_RAMBOOT_SPIFLASH
37 /* High Level Configuration Options */
38 #define CONFIG_BOOKE /* BOOKE */
39 #define CONFIG_E500 /* BOOKE e500 family */
40 #define CONFIG_CONTROLCENTERD
41 #define CONFIG_MP /* support multiple processors */
43 #define CONFIG_SYS_NO_FLASH
44 #define CONFIG_ENABLE_36BIT_PHYS
46 #ifdef CONFIG_PHYS_64BIT
47 #define CONFIG_ADDR_MAP
48 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
51 #define CONFIG_L2_CACHE
54 #define CONFIG_SYS_CLK_FREQ 66666600
55 #define CONFIG_DDR_CLK_FREQ 66666600
57 #define CONFIG_SYS_RAMBOOT
59 #ifdef CONFIG_TRAILBLAZER
61 #define CONFIG_SYS_TEXT_BASE 0xf8fc0000
62 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
63 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
68 #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
69 #ifdef CONFIG_PHYS_64BIT
70 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
72 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
74 #define CONFIG_SYS_L2_SIZE (256 << 10)
75 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
77 #else /* CONFIG_TRAILBLAZER */
79 #define CONFIG_SYS_TEXT_BASE 0x11000000
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
81 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
83 #endif /* CONFIG_TRAILBLAZER */
85 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
86 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
91 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
92 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
93 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
95 * Localbus non-cacheable
96 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
97 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
98 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
99 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
102 #define CONFIG_SYS_INIT_RAM_LOCK
103 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
104 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
105 #define CONFIG_SYS_GBL_DATA_OFFSET \
106 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
107 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
109 #ifdef CONFIG_TRAILBLAZER
110 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
111 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
113 #define CONFIG_SYS_CCSRBAR 0xffe00000
115 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
116 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
122 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
124 #define CONFIG_SYS_SDRAM_SIZE 1024
125 #define CONFIG_VERY_BIG_RAM
127 #define CONFIG_SYS_FSL_DDR3
128 #define CONFIG_NUM_DDR_CONTROLLERS 1
129 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
130 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
132 #define CONFIG_SYS_MEMTEST_START 0x00000000
133 #define CONFIG_SYS_MEMTEST_END 0x3fffffff
135 #ifdef CONFIG_TRAILBLAZER
136 #define CONFIG_SPD_EEPROM
137 #define SPD_EEPROM_ADDRESS 0x52
138 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
142 * Local Bus Definitions
144 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
146 #define CONFIG_SYS_ELBC_BASE 0xe0000000
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
150 #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
153 #define CONFIG_UART_BR_PRELIM \
154 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
155 #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
157 #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
158 #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
160 #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
161 #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
166 #define CONFIG_CONS_INDEX 2
167 #define CONFIG_SYS_NS16550_SERIAL
168 #define CONFIG_SYS_NS16550_REG_SIZE 1
169 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
171 #define CONFIG_SYS_BAUDRATE_TABLE \
172 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
174 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
175 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
180 #define CONFIG_SYS_I2C
181 #define CONFIG_SYS_I2C_FSL
182 #define CONFIG_SYS_FSL_I2C_SPEED 400000
183 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
184 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
185 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
186 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
187 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
189 #ifndef CONFIG_TRAILBLAZER
192 #define CONFIG_PCA9698 /* NXP PCA9698 */
194 #define CONFIG_CMD_EEPROM
195 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
196 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
198 #ifndef CONFIG_TRAILBLAZER
200 * eSPI - Enhanced SPI
202 #define CONFIG_HARD_SPI
204 #define CONFIG_SF_DEFAULT_SPEED 10000000
205 #define CONFIG_SF_DEFAULT_MODE 0
213 #define CONFIG_GENERIC_MMC
215 #define CONFIG_FSL_ESDHC
216 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
218 #ifndef CONFIG_TRAILBLAZER
223 #define CONFIG_FSL_DIU_FB
224 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
225 #define CONFIG_CMD_BMP
229 * Memory space is mapped 1-1, but I/O space must start from 0.
231 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
232 #define CONFIG_PCI_INDIRECT_BRIDGE
233 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
234 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
235 #define CONFIG_CMD_PCI
237 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
238 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
240 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
241 #ifdef CONFIG_PHYS_64BIT
242 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
243 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
245 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
246 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
248 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
249 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
250 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
251 #ifdef CONFIG_PHYS_64BIT
252 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
254 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
256 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
261 #define CONFIG_LIBATA
263 #define CONFIG_CMD_SATA
265 #define CONFIG_FSL_SATA
266 #define CONFIG_SYS_SATA_MAX_DEVICE 2
268 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
269 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
271 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
272 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
277 #define CONFIG_TSEC_ENET
279 #define CONFIG_TSECV2
281 #define CONFIG_MII /* MII PHY management */
282 #define CONFIG_TSEC1 1
283 #define CONFIG_TSEC1_NAME "eTSEC1"
284 #define CONFIG_TSEC2 1
285 #define CONFIG_TSEC2_NAME "eTSEC2"
287 #define TSEC1_PHY_ADDR 0
288 #define TSEC2_PHY_ADDR 1
290 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
291 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
293 #define TSEC1_PHYIDX 0
294 #define TSEC2_PHYIDX 0
296 #define CONFIG_ETHPRIME "eTSEC1"
298 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
303 #define CONFIG_USB_EHCI
305 #define CONFIG_HAS_FSL_DR_USB
306 #define CONFIG_USB_EHCI_FSL
307 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
309 #endif /* CONFIG_TRAILBLAZER */
314 #if defined(CONFIG_TRAILBLAZER)
315 #define CONFIG_ENV_IS_NOWHERE
316 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
317 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
318 #define CONFIG_ENV_IS_IN_SPI_FLASH
319 #define CONFIG_ENV_SPI_BUS 0
320 #define CONFIG_ENV_SPI_CS 0
321 #define CONFIG_ENV_SPI_MAX_HZ 10000000
322 #define CONFIG_ENV_SPI_MODE 0
323 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
324 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
325 #define CONFIG_ENV_SECT_SIZE 0x10000
326 #elif defined(CONFIG_RAMBOOT_SDCARD)
327 #define CONFIG_ENV_IS_IN_MMC
328 #define CONFIG_FSL_FIXED_MMC_LOCATION
329 #define CONFIG_ENV_SIZE 0x2000
330 #define CONFIG_SYS_MMC_ENV_DEV 0
333 #define CONFIG_SYS_EXTRA_ENV_RELOC
336 * Command line configuration.
338 #ifndef CONFIG_TRAILBLAZER
339 #define CONFIG_SYS_LONGHELP
340 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
341 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
342 #endif /* CONFIG_TRAILBLAZER */
344 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
345 #ifdef CONFIG_CMD_KGDB
346 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
348 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
350 /* Print Buffer Size */
351 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
352 #define CONFIG_SYS_MAXARGS 16
353 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
355 #ifndef CONFIG_TRAILBLAZER
357 #define CONFIG_CMD_ERRATA
358 #define CONFIG_CMD_IRQ
359 #define CONFIG_CMD_REGINFO
362 * Board initialisation callbacks
364 #define CONFIG_BOARD_EARLY_INIT_F
365 #define CONFIG_BOARD_EARLY_INIT_R
366 #define CONFIG_MISC_INIT_R
367 #define CONFIG_LAST_STAGE_INIT
369 #else /* CONFIG_TRAILBLAZER */
371 #define CONFIG_BOARD_EARLY_INIT_F
372 #define CONFIG_BOARD_EARLY_INIT_R
373 #define CONFIG_LAST_STAGE_INIT
375 #endif /* CONFIG_TRAILBLAZER */
378 * Miscellaneous configurable options
380 #define CONFIG_HW_WATCHDOG
381 #define CONFIG_LOADS_ECHO
382 #define CONFIG_SYS_LOADS_BAUD_CHANGE
383 #define CONFIG_DOS_PARTITION
386 * For booting Linux, the board info and command line data
387 * have to be in the first 64 MB of memory, since this is
388 * the maximum mapped by the Linux kernel during initialization.
390 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
391 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
394 * Environment Configuration
397 #ifdef CONFIG_TRAILBLAZER
399 #define CONFIG_BAUDRATE 115200
401 #define CONFIG_EXTRA_ENV_SETTINGS \
406 #define CONFIG_HOSTNAME controlcenterd
407 #define CONFIG_ROOTPATH "/opt/nfsroot"
408 #define CONFIG_BOOTFILE "uImage"
409 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
411 #define CONFIG_LOADADDR 1000000
414 #define CONFIG_BAUDRATE 115200
416 #define CONFIG_EXTRA_ENV_SETTINGS \
418 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
419 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
420 "tftpflash=tftpboot $loadaddr $uboot && " \
421 "protect off $ubootaddr +$filesize && " \
422 "erase $ubootaddr +$filesize && " \
423 "cp.b $loadaddr $ubootaddr $filesize && " \
424 "protect on $ubootaddr +$filesize && " \
425 "cmp.b $loadaddr $ubootaddr $filesize\0" \
426 "consoledev=ttyS1\0" \
427 "ramdiskaddr=2000000\0" \
428 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
429 "fdtaddr=1e00000\0" \
430 "fdtfile=controlcenterd.dtb\0" \
433 /* these are used and NUL-terminated in env_default.h */
434 #define CONFIG_NFSBOOTCOMMAND \
435 "setenv bootargs root=/dev/nfs rw " \
436 "nfsroot=$serverip:$rootpath " \
437 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
438 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
439 "tftp $loadaddr $bootfile;" \
440 "tftp $fdtaddr $fdtfile;" \
441 "bootm $loadaddr - $fdtaddr"
443 #define CONFIG_RAMBOOTCOMMAND \
444 "setenv bootargs root=/dev/ram rw " \
445 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
446 "tftp $ramdiskaddr $ramdiskfile;" \
447 "tftp $loadaddr $bootfile;" \
448 "tftp $fdtaddr $fdtfile;" \
449 "bootm $loadaddr $ramdiskaddr $fdtaddr"
451 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
453 #endif /* CONFIG_TRAILBLAZER */