3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <linux/stringify.h>
32 #define CONFIG_RAMBOOT_SDCARD
35 #ifdef CONFIG_SPIFLASH
36 #define CONFIG_RAMBOOT_SPIFLASH
39 /* High Level Configuration Options */
40 #define CONFIG_CONTROLCENTERD
42 #define CONFIG_ENABLE_36BIT_PHYS
44 #ifdef CONFIG_PHYS_64BIT
45 #define CONFIG_ADDR_MAP
46 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
49 #define CONFIG_L2_CACHE
52 #define CONFIG_SYS_CLK_FREQ 66666600
53 #define CONFIG_DDR_CLK_FREQ 66666600
55 #define CONFIG_SYS_RAMBOOT
57 #ifdef CONFIG_TRAILBLAZER
59 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
60 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
65 #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
66 #ifdef CONFIG_PHYS_64BIT
67 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
69 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
71 #define CONFIG_SYS_L2_SIZE (256 << 10)
72 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
74 #else /* CONFIG_TRAILBLAZER */
76 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
77 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
79 #endif /* CONFIG_TRAILBLAZER */
81 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
82 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
87 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
88 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
89 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
91 * Localbus non-cacheable
92 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
93 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
94 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
95 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
98 #define CONFIG_SYS_INIT_RAM_LOCK
99 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
100 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
101 #define CONFIG_SYS_GBL_DATA_OFFSET \
102 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
105 #ifdef CONFIG_TRAILBLAZER
106 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
107 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
109 #define CONFIG_SYS_CCSRBAR 0xffe00000
111 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
112 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
120 #define CONFIG_SYS_SDRAM_SIZE 1024
121 #define CONFIG_VERY_BIG_RAM
123 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
124 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
126 #ifdef CONFIG_TRAILBLAZER
127 #define CONFIG_SPD_EEPROM
128 #define SPD_EEPROM_ADDRESS 0x52
129 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
133 * Local Bus Definitions
136 #define CONFIG_SYS_ELBC_BASE 0xe0000000
137 #ifdef CONFIG_PHYS_64BIT
138 #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
140 #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
143 #define CONFIG_UART_BR_PRELIM \
144 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
145 #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
147 #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
148 #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
150 #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
151 #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
156 #define CONFIG_SYS_NS16550_SERIAL
157 #define CONFIG_SYS_NS16550_REG_SIZE 1
158 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
160 #define CONFIG_SYS_BAUDRATE_TABLE \
161 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
163 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
164 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
169 #define CONFIG_SYS_I2C
170 #define CONFIG_SYS_I2C_FSL
171 #define CONFIG_SYS_FSL_I2C_SPEED 400000
172 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
173 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
174 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
175 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
176 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
178 #define CONFIG_PCA9698 /* NXP PCA9698 */
180 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
181 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
186 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
188 #ifndef CONFIG_TRAILBLAZER
193 #define CONFIG_FSL_DIU_FB
194 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
198 * Memory space is mapped 1-1, but I/O space must start from 0.
200 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
201 #define CONFIG_PCI_INDIRECT_BRIDGE
202 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
203 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
205 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
207 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
208 #ifdef CONFIG_PHYS_64BIT
209 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
210 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
212 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
213 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
215 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
216 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
217 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
218 #ifdef CONFIG_PHYS_64BIT
219 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
221 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
223 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
230 #define CONFIG_SYS_SATA_MAX_DEVICE 2
232 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
233 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
235 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
236 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
242 #define CONFIG_TSECV2
244 #define CONFIG_TSEC1 1
245 #define CONFIG_TSEC1_NAME "eTSEC1"
246 #define CONFIG_TSEC2 1
247 #define CONFIG_TSEC2_NAME "eTSEC2"
249 #define TSEC1_PHY_ADDR 0
250 #define TSEC2_PHY_ADDR 1
252 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
253 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
255 #define TSEC1_PHYIDX 0
256 #define TSEC2_PHYIDX 0
258 #define CONFIG_ETHPRIME "eTSEC1"
264 #define CONFIG_HAS_FSL_DR_USB
265 #define CONFIG_USB_EHCI_FSL
266 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
268 #endif /* CONFIG_TRAILBLAZER */
273 #if defined(CONFIG_TRAILBLAZER)
274 #elif defined(CONFIG_RAMBOOT_SDCARD)
275 #define CONFIG_FSL_FIXED_MMC_LOCATION
276 #define CONFIG_SYS_MMC_ENV_DEV 0
280 * Command line configuration.
283 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
285 #ifndef CONFIG_TRAILBLAZER
287 * Board initialisation callbacks
289 #endif /* CONFIG_TRAILBLAZER */
292 * Miscellaneous configurable options
294 #define CONFIG_HW_WATCHDOG
295 #define CONFIG_LOADS_ECHO
296 #define CONFIG_SYS_LOADS_BAUD_CHANGE
299 * For booting Linux, the board info and command line data
300 * have to be in the first 64 MB of memory, since this is
301 * the maximum mapped by the Linux kernel during initialization.
303 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
304 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
307 * Environment Configuration
310 #ifdef CONFIG_TRAILBLAZER
311 #define CONFIG_EXTRA_ENV_SETTINGS \
316 #define CONFIG_HOSTNAME "controlcenterd"
317 #define CONFIG_ROOTPATH "/opt/nfsroot"
318 #define CONFIG_BOOTFILE "uImage"
319 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
321 #define CONFIG_LOADADDR 1000000
323 #define CONFIG_EXTRA_ENV_SETTINGS \
325 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
326 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
327 "tftpflash=tftpboot $loadaddr $uboot && " \
328 "protect off $ubootaddr +$filesize && " \
329 "erase $ubootaddr +$filesize && " \
330 "cp.b $loadaddr $ubootaddr $filesize && " \
331 "protect on $ubootaddr +$filesize && " \
332 "cmp.b $loadaddr $ubootaddr $filesize\0" \
333 "consoledev=ttyS1\0" \
334 "ramdiskaddr=2000000\0" \
335 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
336 "fdtaddr=1e00000\0" \
337 "fdtfile=controlcenterd.dtb\0" \
340 /* these are used and NUL-terminated in env_default.h */
341 #define CONFIG_NFSBOOTCOMMAND \
342 "setenv bootargs root=/dev/nfs rw " \
343 "nfsroot=$serverip:$rootpath " \
344 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
345 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
346 "tftp $loadaddr $bootfile;" \
347 "tftp $fdtaddr $fdtfile;" \
348 "bootm $loadaddr - $fdtaddr"
350 #define CONFIG_RAMBOOTCOMMAND \
351 "setenv bootargs root=/dev/ram rw " \
352 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
353 "tftp $ramdiskaddr $ramdiskfile;" \
354 "tftp $loadaddr $bootfile;" \
355 "tftp $fdtaddr $fdtfile;" \
356 "bootm $loadaddr $ramdiskaddr $fdtaddr"
358 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
360 #endif /* CONFIG_TRAILBLAZER */