Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
[platform/kernel/u-boot.git] / include / configs / controlcenterd.h
1 /*
2  * (C) Copyright 2013
3  * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4  *
5  * based on P1022DS.h
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25
26 #ifndef __CONFIG_H
27 #define __CONFIG_H
28
29 #ifdef CONFIG_SDCARD
30 #define CONFIG_RAMBOOT_SDCARD
31 #endif
32
33 #ifdef CONFIG_SPIFLASH
34 #define CONFIG_RAMBOOT_SPIFLASH
35 #endif
36
37 /* High Level Configuration Options */
38 #define CONFIG_CONTROLCENTERD
39
40 #define CONFIG_ENABLE_36BIT_PHYS
41
42 #ifdef CONFIG_PHYS_64BIT
43 #define CONFIG_ADDR_MAP
44 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
45 #endif
46
47 #define CONFIG_L2_CACHE
48 #define CONFIG_BTB
49
50 #define CONFIG_SYS_CLK_FREQ     66666600
51 #define CONFIG_DDR_CLK_FREQ     66666600
52
53 #define CONFIG_SYS_RAMBOOT
54
55 #ifdef CONFIG_TRAILBLAZER
56
57 #define CONFIG_RESET_VECTOR_ADDRESS     0xf8fffffc
58 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
59
60 /*
61  * Config the L2 Cache
62  */
63 #define CONFIG_SYS_INIT_L2_ADDR         0xf8fc0000
64 #ifdef CONFIG_PHYS_64BIT
65 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    0xff8fc0000ull
66 #else
67 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
68 #endif
69 #define CONFIG_SYS_L2_SIZE              (256 << 10)
70 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
71
72 #else /* CONFIG_TRAILBLAZER */
73
74 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
75 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
76
77 #endif /* CONFIG_TRAILBLAZER */
78
79 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
80 #define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
81
82 /*
83  * Memory map
84  *
85  * 0x0000_0000  0x3fff_ffff     DDR                     1G Cacheable
86  * 0xc000_0000  0xdfff_ffff     PCI Express Mem         512M non-cacheable
87  * 0xffc0_0000  0xffc2_ffff     PCI IO range            192K non-cacheable
88  *
89  * Localbus non-cacheable
90  * 0xe000_0000  0xe00f_ffff     eLBC                    1M non-cacheable
91  * 0xf8fc0000   0xf8ff_ffff     L2 SRAM                 256k Cacheable
92  * 0xffd0_0000  0xffd0_3fff     L1 for stack            16K Cacheable TLB0
93  * 0xffe0_0000  0xffef_ffff     CCSR                    1M non-cacheable
94  */
95
96 #define CONFIG_SYS_INIT_RAM_LOCK
97 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* Initial L1 address */
98 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* used area in RAM */
99 #define CONFIG_SYS_GBL_DATA_OFFSET      \
100         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
101 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
102
103 #ifdef CONFIG_TRAILBLAZER
104 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
105 #define CONFIG_SYS_CCSRBAR              CONFIG_SYS_CCSRBAR_DEFAULT
106 #else
107 #define CONFIG_SYS_CCSRBAR              0xffe00000
108 #endif
109 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
110 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR   (CONFIG_SYS_CCSRBAR+0xf200)
111
112 /*
113  * DDR Setup
114  */
115
116 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
117 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
118 #define CONFIG_SYS_SDRAM_SIZE 1024
119 #define CONFIG_VERY_BIG_RAM
120
121 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
122 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
123
124 #define CONFIG_SYS_MEMTEST_START        0x00000000
125 #define CONFIG_SYS_MEMTEST_END          0x3fffffff
126
127 #ifdef CONFIG_TRAILBLAZER
128 #define CONFIG_SPD_EEPROM
129 #define SPD_EEPROM_ADDRESS 0x52
130 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
131 #endif
132
133 /*
134  * Local Bus Definitions
135  */
136
137 #define CONFIG_SYS_ELBC_BASE            0xe0000000
138 #ifdef CONFIG_PHYS_64BIT
139 #define CONFIG_SYS_ELBC_BASE_PHYS       0xfe0000000ull
140 #else
141 #define CONFIG_SYS_ELBC_BASE_PHYS       CONFIG_SYS_ELBC_BASE
142 #endif
143
144 #define CONFIG_UART_BR_PRELIM  \
145         (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
146 #define CONFIG_UART_OR_PRELIM   (OR_AM_32KB | 0xff7)
147
148 #define CONFIG_SYS_BR0_PRELIM   0 /* CS0 was originally intended for FPGA */
149 #define CONFIG_SYS_OR0_PRELIM   0 /* debugging, was never used */
150
151 #define CONFIG_SYS_BR1_PRELIM   CONFIG_UART_BR_PRELIM
152 #define CONFIG_SYS_OR1_PRELIM   CONFIG_UART_OR_PRELIM
153
154 /*
155  * Serial Port
156  */
157 #define CONFIG_SYS_NS16550_SERIAL
158 #define CONFIG_SYS_NS16550_REG_SIZE     1
159 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
160
161 #define CONFIG_SYS_BAUDRATE_TABLE       \
162         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
163
164 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
165 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
166
167 /*
168  * I2C
169  */
170 #define CONFIG_SYS_I2C
171 #define CONFIG_SYS_I2C_FSL
172 #define CONFIG_SYS_FSL_I2C_SPEED        400000
173 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
174 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
175 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
176 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
177 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
178
179 #define CONFIG_PCA9698                  /* NXP PCA9698 */
180
181 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
183
184 /*
185  * MMC
186  */
187 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
188
189 #ifndef CONFIG_TRAILBLAZER
190
191 /*
192  * Video
193  */
194 #define CONFIG_FSL_DIU_FB
195 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x10000)
196
197 /*
198  * General PCI
199  * Memory space is mapped 1-1, but I/O space must start from 0.
200  */
201 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
202 #define CONFIG_PCI_INDIRECT_BRIDGE
203 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
204 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
205
206 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
207
208 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
209 #ifdef CONFIG_PHYS_64BIT
210 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
211 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc40000000ull
212 #else
213 #define CONFIG_SYS_PCIE1_MEM_BUS        0xc0000000
214 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc0000000
215 #endif
216 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
217 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
218 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
219 #ifdef CONFIG_PHYS_64BIT
220 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc20000ull
221 #else
222 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc20000
223 #endif
224 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
225
226 /*
227  * SATA
228  */
229 #define CONFIG_LBA48
230
231 #define CONFIG_SYS_SATA_MAX_DEVICE      2
232 #define CONFIG_SATA1
233 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
234 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
235 #define CONFIG_SATA2
236 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
237 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
238
239 /*
240  * Ethernet
241  */
242
243 #define CONFIG_TSECV2
244
245 #define CONFIG_TSEC1            1
246 #define CONFIG_TSEC1_NAME       "eTSEC1"
247 #define CONFIG_TSEC2            1
248 #define CONFIG_TSEC2_NAME       "eTSEC2"
249
250 #define TSEC1_PHY_ADDR          0
251 #define TSEC2_PHY_ADDR          1
252
253 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
254 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
255
256 #define TSEC1_PHYIDX            0
257 #define TSEC2_PHYIDX            0
258
259 #define CONFIG_ETHPRIME         "eTSEC1"
260
261 /*
262  * USB
263  */
264
265 #define CONFIG_HAS_FSL_DR_USB
266 #define CONFIG_USB_EHCI_FSL
267 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
268
269 #endif /* CONFIG_TRAILBLAZER */
270
271 /*
272  * Environment
273  */
274 #if defined(CONFIG_TRAILBLAZER)
275 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
276 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
277 #define CONFIG_ENV_SIZE         0x2000          /* 8KB */
278 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
279 #define CONFIG_ENV_SECT_SIZE    0x10000
280 #elif defined(CONFIG_RAMBOOT_SDCARD)
281 #define CONFIG_FSL_FIXED_MMC_LOCATION
282 #define CONFIG_ENV_SIZE         0x2000
283 #define CONFIG_SYS_MMC_ENV_DEV  0
284 #endif
285
286 /*
287  * Command line configuration.
288  */
289
290 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
291
292 #ifndef CONFIG_TRAILBLAZER
293 /*
294  * Board initialisation callbacks
295  */
296 #endif /* CONFIG_TRAILBLAZER */
297
298 /*
299  * Miscellaneous configurable options
300  */
301 #define CONFIG_HW_WATCHDOG
302 #define CONFIG_LOADS_ECHO
303 #define CONFIG_SYS_LOADS_BAUD_CHANGE
304
305 /*
306  * For booting Linux, the board info and command line data
307  * have to be in the first 64 MB of memory, since this is
308  * the maximum mapped by the Linux kernel during initialization.
309  */
310 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Linux Memory map */
311 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
312
313 /*
314  * Environment Configuration
315  */
316
317 #ifdef CONFIG_TRAILBLAZER
318 #define CONFIG_EXTRA_ENV_SETTINGS                               \
319         "mp_holdoff=1\0"
320
321 #else
322
323 #define CONFIG_HOSTNAME         "controlcenterd"
324 #define CONFIG_ROOTPATH         "/opt/nfsroot"
325 #define CONFIG_BOOTFILE         "uImage"
326 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP */
327
328 #define CONFIG_LOADADDR         1000000
329
330 #define CONFIG_EXTRA_ENV_SETTINGS                               \
331         "netdev=eth0\0"                                         \
332         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
333         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
334         "tftpflash=tftpboot $loadaddr $uboot && "               \
335                 "protect off $ubootaddr +$filesize && "         \
336                 "erase $ubootaddr +$filesize && "               \
337                 "cp.b $loadaddr $ubootaddr $filesize && "       \
338                 "protect on $ubootaddr +$filesize && "          \
339                 "cmp.b $loadaddr $ubootaddr $filesize\0"        \
340         "consoledev=ttyS1\0"                                    \
341         "ramdiskaddr=2000000\0"                                 \
342         "ramdiskfile=rootfs.ext2.gz.uboot\0"                    \
343         "fdtaddr=1e00000\0"                                     \
344         "fdtfile=controlcenterd.dtb\0"                          \
345         "bdev=sda3\0"
346
347 /* these are used and NUL-terminated in env_default.h */
348 #define CONFIG_NFSBOOTCOMMAND                                           \
349         "setenv bootargs root=/dev/nfs rw "                             \
350         "nfsroot=$serverip:$rootpath "                                  \
351         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
352         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
353         "tftp $loadaddr $bootfile;"                                     \
354         "tftp $fdtaddr $fdtfile;"                                       \
355         "bootm $loadaddr - $fdtaddr"
356
357 #define CONFIG_RAMBOOTCOMMAND                                           \
358         "setenv bootargs root=/dev/ram rw "                             \
359         "console=$consoledev,$baudrate $othbootargs $videobootargs;"    \
360         "tftp $ramdiskaddr $ramdiskfile;"                               \
361         "tftp $loadaddr $bootfile;"                                     \
362         "tftp $fdtaddr $fdtfile;"                                       \
363         "bootm $loadaddr $ramdiskaddr $fdtaddr"
364
365 #define CONFIG_BOOTCOMMAND              CONFIG_RAMBOOTCOMMAND
366
367 #endif /* CONFIG_TRAILBLAZER */
368
369 #endif