1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015-2019 Toradex, Inc.
5 * Configuration settings for the Toradex VF50/VF61 modules.
8 * Copyright 2013 Freescale Semiconductor, Inc.
14 #include <asm/arch/imx-regs.h>
15 #include <linux/sizes.h>
17 #define CONFIG_SYS_FSL_CLK
19 #define CONFIG_SKIP_LOWLEVEL_INIT
21 #ifdef CONFIG_VIDEO_FSL_DCU_FB
22 #define CONFIG_SPLASH_SCREEN_ALIGN
23 #define CONFIG_VIDEO_LOGO
24 #define CONFIG_VIDEO_BMP_LOGO
25 #define CONFIG_SYS_FSL_DCU_LE
27 #define CONFIG_SYS_DCU_ADDR DCU0_BASE_ADDR
28 #define DCU_LAYER_MAX_NUM 64
31 /* Size of malloc() pool */
32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M)
34 /* Allow to overwrite serial and ethaddr */
35 #define CONFIG_ENV_OVERWRITE
38 #define CONFIG_SYS_NAND_ONFI_DETECTION
39 #define CONFIG_SYS_MAX_NAND_DEVICE 1
41 #define CONFIG_IPADDR 192.168.10.2
42 #define CONFIG_NETMASK 255.255.255.0
43 #define CONFIG_SERVERIP 192.168.10.1
45 #define CONFIG_LOADADDR 0x80008000
46 #define CONFIG_FDTADDR 0x84000000
48 /* We boot from the gfxRAM area of the OCRAM. */
49 #define CONFIG_BOARD_SIZE_LIMIT 520192
51 #define MEM_LAYOUT_ENV_SETTINGS \
52 "bootm_size=0x10000000\0" \
53 "fdt_addr_r=0x82000000\0" \
54 "fdt_high=0xffffffff\0" \
55 "initrd_high=0xffffffff\0" \
56 "kernel_addr_r=0x81000000\0" \
57 "pxefile_addr_r=0x87100000\0" \
58 "ramdisk_addr_r=0x82100000\0" \
59 "scriptaddr=0x87000000\0"
62 "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
63 "nfsboot=run setup; " \
64 "setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \
65 "${setupargs} ${vidargs}; echo Booting from NFS...;" \
66 "dhcp ${kernel_addr_r} && " \
67 "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
68 "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
71 "set_sdargs=setenv sdargs root=PARTUUID=${uuid} ro rootwait\0" \
72 "sdboot=run setup; run sdfinduuid; run set_sdargs; " \
73 "setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
74 "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
75 "load mmc ${sddev}:${sdbootpart} ${kernel_addr_r} ${kernel_file} && " \
76 "load mmc ${sddev}:${sdbootpart} ${fdt_addr_r} " \
77 "${soc}-colibri-${fdt_board}.dtb && " \
78 "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
81 "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
86 "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
87 "ubi.fm_autoconvert=1\0" \
88 "ubiboot=run setup; " \
89 "setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \
90 "${setupargs} ${vidargs}; echo Booting from NAND...; " \
92 "ubi read ${kernel_addr_r} kernel && " \
93 "ubi read ${fdt_addr_r} dtb && " \
94 "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
96 #define CONFIG_BOOTCOMMAND "run ubiboot; " \
97 "setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;"
99 #define BOOT_TARGET_DEVICES(func) \
103 #include <config_distro_bootcmd.h>
104 #undef BOOTENV_RUN_NET_USB_START
105 #define BOOTENV_RUN_NET_USB_START ""
107 #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4"
109 #define CONFIG_EXTRA_ENV_SETTINGS \
111 MEM_LAYOUT_ENV_SETTINGS \
116 "defargs=user_debug=30\0" \
117 "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
118 "fdt_board=eval-v3\0" \
120 "kernel_file=zImage\0" \
121 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
122 "setsdupdate=mmc rescan && set interface mmc && " \
123 "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
124 "source ${loadaddr}\0" \
125 "setup=setenv setupargs console=tty1 console=${console}" \
126 ",${baudrate}n8 ${memargs}\0" \
127 "setupdate=run setsdupdate || run setusbupdate\0" \
128 "setusbupdate=usb start && set interface usb && " \
129 "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
130 "source ${loadaddr}\0" \
132 "video-mode=dcufb:640x480-16@60,monitor=lcd\0"
134 /* Miscellaneous configurable options */
135 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
136 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
138 #define CONFIG_SYS_MEMTEST_START 0x80010000
139 #define CONFIG_SYS_MEMTEST_END 0x87C00000
141 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
142 #define CONFIG_SYS_HZ 1000
144 /* Physical memory map */
145 #define PHYS_SDRAM (0x80000000)
146 #define PHYS_SDRAM_SIZE (256 * SZ_1M)
148 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
149 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
150 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
152 #define CONFIG_SYS_INIT_SP_OFFSET \
153 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 #define CONFIG_SYS_INIT_SP_ADDR \
155 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
157 /* Environment organization */
158 #ifdef CONFIG_ENV_IS_IN_NAND
159 #define CONFIG_ENV_RANGE (4 * 64 * 2048)
162 /* USB Host Support */
163 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
164 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
167 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
169 #endif /* __CONFIG_H */