include/configs/colibri_pxa270.h

   1 /*
   2  * Toradex Colibri PXA270 configuration file
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Board Configuration Options
  15  */
  16 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  17 /* Avoid overwriting factory configuration block */
  18 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  19
  20 /* We will never enable dcache because we have to setup MMU first */
  21 #define CONFIG_SYS_DCACHE_OFF
  22
  23 #define CONFIG_DISPLAY_BOARDINFO_LATE   /* Calls show_board_info() */
  24
  25 /*
  26  * Environment settings
  27  */
  28 #define CONFIG_ENV_OVERWRITE
  29 #define CONFIG_ENV_VARS_UBOOT_CONFIG
  30 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  31 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  32 #define CONFIG_ARCH_CPU_INIT
  33 #define CONFIG_BOOTCOMMAND                                              \
  34         "if fatload mmc 0 0xa0000000 uImage; then "                     \
  35                 "bootm 0xa0000000; "                                    \
  36         "fi; "                                                          \
  37         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
  38                 "bootm 0xa0000000; "                                    \
  39         "fi; "                                                          \
  40         "bootm 0xc0000;"
  41 #define CONFIG_TIMESTAMP
  42 #define CONFIG_CMDLINE_TAG
  43 #define CONFIG_SETUP_MEMORY_TAGS
  44
  45 /*
  46  * Serial Console Configuration
  47  */
  48
  49 /*
  50  * Bootloader Components Configuration
  51  */
  52
  53 /* I2C support */
  54 #ifdef CONFIG_SYS_I2C
  55 #define CONFIG_SYS_I2C_PXA
  56 #define CONFIG_PXA_STD_I2C
  57 #define CONFIG_PXA_PWR_I2C
  58 #define CONFIG_SYS_I2C_SPEED            100000
  59 #endif
  60
  61 /* LCD support */
  62 #ifdef CONFIG_LCD
  63 #define CONFIG_PXA_LCD
  64 #define CONFIG_PXA_VGA
  65 #define CONFIG_LCD_LOGO
  66 #endif
  67
  68 /*
  69  * Networking Configuration
  70  */
  71 #ifdef  CONFIG_CMD_NET
  72
  73 #define CONFIG_DRIVER_DM9000            1
  74 #define CONFIG_DM9000_BASE              0x08000000
  75 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  76 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  77 #define CONFIG_NET_RETRY_COUNT          10
  78
  79 #define CONFIG_BOOTP_BOOTFILESIZE
  80 #define CONFIG_BOOTP_BOOTPATH
  81 #define CONFIG_BOOTP_GATEWAY
  82 #define CONFIG_BOOTP_HOSTNAME
  83 #endif
  84
  85 #undef  CONFIG_SYS_LONGHELP             /* Saves 10 KB */
  86 #define CONFIG_SYS_DEVICE_NULLDEV       1
  87 #undef  CONFIG_CMDLINE_EDITING          /* Saves 2.5 KB */
  88 #undef  CONFIG_AUTO_COMPLETE            /* Saves 2.5 KB */
  89
  90 /*
  91  * Clock Configuration
  92  */
  93 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  94
  95 /*
  96  * DRAM Map
  97  */
  98 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
  99 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 100 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
 101
 102 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 103 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
 104
 105 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 106 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 107
 108 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
 109 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 110 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
 111
 112 /*
 113  * NOR FLASH
 114  */
 115 #ifdef  CONFIG_CMD_FLASH
 116 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 117 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
 118 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 119
 120 #define CONFIG_SYS_FLASH_CFI
 121 #define CONFIG_FLASH_CFI_DRIVER         1
 122 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
 123
 124 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
 125 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 126
 127 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
 128 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
 129 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
 130 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
 131
 132 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 133 #define CONFIG_SYS_FLASH_PROTECTION             1
 134 #endif
 135
 136 #define CONFIG_SYS_MONITOR_BASE         0x0
 137 #define CONFIG_SYS_MONITOR_LEN          0x40000
 138
 139 /* Skip factory configuration block */
 140 #define CONFIG_ENV_ADDR                 \
 141                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
 142 #define CONFIG_ENV_SIZE                 0x40000
 143 #define CONFIG_ENV_SECT_SIZE            0x40000
 144
 145 /*
 146  * GPIO settings
 147  */
 148 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 149 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 150 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
 151 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 152
 153 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 154 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 155 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 156 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 157
 158 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 159 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 160 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 161 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 162
 163 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 164 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 165 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 166 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 167 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 168 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 169 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 170 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 171
 172 #define CONFIG_SYS_PSSR_VAL     0x30
 173
 174 /*
 175  * Clock settings
 176  */
 177 #define CONFIG_SYS_CKEN         0x00500240
 178 #define CONFIG_SYS_CCCR         0x02000290
 179
 180 /*
 181  * Memory settings
 182  */
 183 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 184 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 185 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 186 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 187 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 188 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 189 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 190 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 191
 192 /*
 193  * PCMCIA and CF Interfaces
 194  */
 195 #define CONFIG_SYS_MECR_VAL     0x00000000
 196 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 197 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 198 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 199 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 200 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 201 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 202
 203 #include "pxa-common.h"
 204
 205 #endif /* __CONFIG_H */