include/configs/colibri_pxa270.h

   1 /*
   2  * Toradex Colibri PXA270 configuration file
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Board Configuration Options
  15  */
  16 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  17 /* Avoid overwriting factory configuration block */
  18 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  19
  20 /* We will never enable dcache because we have to setup MMU first */
  21 #define CONFIG_SYS_DCACHE_OFF
  22
  23 #define CONFIG_DISPLAY_BOARDINFO_LATE   /* Calls show_board_info() */
  24
  25 /*
  26  * Environment settings
  27  */
  28 #define CONFIG_ENV_OVERWRITE
  29 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  30 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  31 #define CONFIG_ARCH_CPU_INIT
  32 #define CONFIG_BOOTCOMMAND                                              \
  33         "if fatload mmc 0 0xa0000000 uImage; then "                     \
  34                 "bootm 0xa0000000; "                                    \
  35         "fi; "                                                          \
  36         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
  37                 "bootm 0xa0000000; "                                    \
  38         "fi; "                                                          \
  39         "bootm 0xc0000;"
  40 #define CONFIG_TIMESTAMP
  41 #define CONFIG_CMDLINE_TAG
  42 #define CONFIG_SETUP_MEMORY_TAGS
  43
  44 /*
  45  * Serial Console Configuration
  46  */
  47
  48 /*
  49  * Bootloader Components Configuration
  50  */
  51
  52 /* I2C support */
  53 #ifdef CONFIG_SYS_I2C
  54 #define CONFIG_SYS_I2C_PXA
  55 #define CONFIG_PXA_STD_I2C
  56 #define CONFIG_PXA_PWR_I2C
  57 #define CONFIG_SYS_I2C_SPEED            100000
  58 #endif
  59
  60 /* LCD support */
  61 #ifdef CONFIG_LCD
  62 #define CONFIG_PXA_LCD
  63 #define CONFIG_PXA_VGA
  64 #define CONFIG_LCD_LOGO
  65 #endif
  66
  67 /*
  68  * Networking Configuration
  69  */
  70 #ifdef  CONFIG_CMD_NET
  71
  72 #define CONFIG_DRIVER_DM9000            1
  73 #define CONFIG_DM9000_BASE              0x08000000
  74 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  75 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  76 #define CONFIG_NET_RETRY_COUNT          10
  77
  78 #define CONFIG_BOOTP_BOOTFILESIZE
  79 #endif
  80
  81 #define CONFIG_SYS_DEVICE_NULLDEV       1
  82
  83 /*
  84  * Clock Configuration
  85  */
  86 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  87
  88 /*
  89  * DRAM Map
  90  */
  91 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
  92 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
  93 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
  94
  95 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
  96 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
  97
  98 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
  99 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 100
 101 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
 102 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 103 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
 104
 105 /*
 106  * NOR FLASH
 107  */
 108 #ifdef  CONFIG_CMD_FLASH
 109 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 110 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
 111 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 112
 113 #define CONFIG_SYS_FLASH_CFI
 114 #define CONFIG_FLASH_CFI_DRIVER         1
 115 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
 116
 117 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
 118 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 119
 120 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
 121 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
 122 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
 123 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
 124
 125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 126 #define CONFIG_SYS_FLASH_PROTECTION             1
 127 #endif
 128
 129 #define CONFIG_SYS_MONITOR_BASE         0x0
 130 #define CONFIG_SYS_MONITOR_LEN          0x40000
 131
 132 /* Skip factory configuration block */
 133 #define CONFIG_ENV_ADDR                 \
 134                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
 135 #define CONFIG_ENV_SIZE                 0x40000
 136 #define CONFIG_ENV_SECT_SIZE            0x40000
 137
 138 /*
 139  * GPIO settings
 140  */
 141 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 142 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 143 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
 144 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 145
 146 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 147 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 148 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 149 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 150
 151 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 152 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 153 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 154 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 155
 156 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 157 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 158 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 159 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 160 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 161 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 162 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 163 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 164
 165 #define CONFIG_SYS_PSSR_VAL     0x30
 166
 167 /*
 168  * Clock settings
 169  */
 170 #define CONFIG_SYS_CKEN         0x00500240
 171 #define CONFIG_SYS_CCCR         0x02000290
 172
 173 /*
 174  * Memory settings
 175  */
 176 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 177 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 178 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 179 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 180 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 181 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 182 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 183 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 184
 185 /*
 186  * PCMCIA and CF Interfaces
 187  */
 188 #define CONFIG_SYS_MECR_VAL     0x00000000
 189 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 190 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 191 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 192 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 193 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 194 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 195
 196 #include "pxa-common.h"
 197
 198 #endif /* __CONFIG_H */