common: bootdelay: move CONFIG_BOOTDELAY into a Kconfig option
[platform/kernel/u-boot.git] / include / configs / colibri_pxa270.h
1 /*
2  * Toradex Colibri PXA270 configuration file
3  *
4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5  * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * High Level Board Configuration Options
15  */
16 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
17 #define CONFIG_SYS_TEXT_BASE            0x0
18 /* Avoid overwriting factory configuration block */
19 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
20
21 /* We will never enable dcache because we have to setup MMU first */
22 #define CONFIG_SYS_DCACHE_OFF
23
24 /*
25  * Environment settings
26  */
27 #define CONFIG_ENV_OVERWRITE
28 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
29 #define CONFIG_ARCH_CPU_INIT
30 #define CONFIG_BOOTCOMMAND                                              \
31         "if fatload mmc 0 0xa0000000 uImage; then "                     \
32                 "bootm 0xa0000000; "                                    \
33         "fi; "                                                          \
34         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
35                 "bootm 0xa0000000; "                                    \
36         "fi; "                                                          \
37         "bootm 0xc0000;"
38 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,115200"
39 #define CONFIG_TIMESTAMP
40 #define CONFIG_CMDLINE_TAG
41 #define CONFIG_SETUP_MEMORY_TAGS
42 #define CONFIG_LZMA                     /* LZMA compression support */
43
44 /*
45  * Serial Console Configuration
46  */
47 #define CONFIG_PXA_SERIAL
48 #define CONFIG_FFUART                   1
49 #define CONFIG_CONS_INDEX               3
50 #define CONFIG_BAUDRATE                 115200
51
52 /*
53  * Bootloader Components Configuration
54  */
55 #define CONFIG_CMD_ENV
56
57 /* I2C support */
58 #ifdef CONFIG_SYS_I2C
59 #define CONFIG_SYS_I2C_PXA
60 #define CONFIG_PXA_STD_I2C
61 #define CONFIG_PXA_PWR_I2C
62 #define CONFIG_SYS_I2C_SPEED            100000
63 #endif
64
65 /* LCD support */
66 #ifdef CONFIG_LCD
67 #define CONFIG_PXA_LCD
68 #define CONFIG_PXA_VGA
69 #define CONFIG_SYS_WHITE_ON_BLACK
70 #define CONFIG_CONSOLE_SCROLL_LINES     10
71 #define CONFIG_CMD_BMP
72 #define CONFIG_LCD_LOGO
73 #endif
74
75 /*
76  * Networking Configuration
77  */
78 #ifdef  CONFIG_CMD_NET
79
80 #define CONFIG_DRIVER_DM9000            1
81 #define CONFIG_DM9000_BASE              0x08000000
82 #define DM9000_IO                       (CONFIG_DM9000_BASE)
83 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
84 #define CONFIG_NET_RETRY_COUNT          10
85
86 #define CONFIG_BOOTP_BOOTFILESIZE
87 #define CONFIG_BOOTP_BOOTPATH
88 #define CONFIG_BOOTP_GATEWAY
89 #define CONFIG_BOOTP_HOSTNAME
90 #endif
91
92 #undef  CONFIG_SYS_LONGHELP             /* Saves 10 KB */
93 #define CONFIG_SYS_CBSIZE               256
94 #define CONFIG_SYS_PBSIZE               \
95         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
96 #define CONFIG_SYS_MAXARGS              16
97 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
98 #define CONFIG_SYS_DEVICE_NULLDEV       1
99 #define CONFIG_CMDLINE_EDITING          1
100 #define CONFIG_AUTO_COMPLETE            1
101
102 /*
103  * Clock Configuration
104  */
105 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
106
107 /*
108  * DRAM Map
109  */
110 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
111 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
112 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
113
114 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
115 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
116
117 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
119
120 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
121 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
122 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
123
124 /*
125  * NOR FLASH
126  */
127 #ifdef  CONFIG_CMD_FLASH
128 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
129 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
130 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
131
132 #define CONFIG_SYS_FLASH_CFI
133 #define CONFIG_FLASH_CFI_DRIVER         1
134 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
135
136 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
137 #define CONFIG_SYS_MAX_FLASH_BANKS      1
138
139 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
140 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
141 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
142 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
143
144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
145 #define CONFIG_SYS_FLASH_PROTECTION             1
146
147 #define CONFIG_ENV_IS_IN_FLASH          1
148
149 #else   /* No flash */
150 #define CONFIG_SYS_NO_FLASH
151 #define CONFIG_ENV_IS_NOWHERE
152 #endif
153
154 #define CONFIG_SYS_MONITOR_BASE         0x0
155 #define CONFIG_SYS_MONITOR_LEN          0x40000
156
157 /* Skip factory configuration block */
158 #define CONFIG_ENV_ADDR                 \
159                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
160 #define CONFIG_ENV_SIZE                 0x40000
161 #define CONFIG_ENV_SECT_SIZE            0x40000
162
163 /*
164  * GPIO settings
165  */
166 #define CONFIG_SYS_GPSR0_VAL    0x00000000
167 #define CONFIG_SYS_GPSR1_VAL    0x00020000
168 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
169 #define CONFIG_SYS_GPSR3_VAL    0x00000000
170
171 #define CONFIG_SYS_GPCR0_VAL    0x00000000
172 #define CONFIG_SYS_GPCR1_VAL    0x00000000
173 #define CONFIG_SYS_GPCR2_VAL    0x00000000
174 #define CONFIG_SYS_GPCR3_VAL    0x00000000
175
176 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
177 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
178 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
179 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
180
181 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
182 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
183 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
184 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
185 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
186 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
187 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
188 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
189
190 #define CONFIG_SYS_PSSR_VAL     0x30
191
192 /*
193  * Clock settings
194  */
195 #define CONFIG_SYS_CKEN         0x00500240
196 #define CONFIG_SYS_CCCR         0x02000290
197
198 /*
199  * Memory settings
200  */
201 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
202 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
203 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
204 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
205 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
206 #define CONFIG_SYS_MDMRS_VAL    0x00220022
207 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
208 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
209
210 /*
211  * PCMCIA and CF Interfaces
212  */
213 #define CONFIG_SYS_MECR_VAL     0x00000000
214 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
215 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
216 #define CONFIG_SYS_MCATT0_VAL   0x00038787
217 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
218 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
219 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
220
221 #include "pxa-common.h"
222
223 #endif /* __CONFIG_H */