include/configs/colibri_pxa270.h

   1 /*
   2  * Toradex Colibri PXA270 configuration file
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Board Configuration Options
  15  */
  16 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  17 #define CONFIG_SYS_TEXT_BASE            0x0
  18 /* Avoid overwriting factory configuration block */
  19 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  20
  21 /* We will never enable dcache because we have to setup MMU first */
  22 #define CONFIG_SYS_DCACHE_OFF
  23
  24 #define CONFIG_DISPLAY_BOARDINFO_LATE   /* Calls show_board_info() */
  25
  26 /*
  27  * Environment settings
  28  */
  29 #define CONFIG_ENV_OVERWRITE
  30 #define CONFIG_ENV_VARS_UBOOT_CONFIG
  31 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  32 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  33 #define CONFIG_ARCH_CPU_INIT
  34 #define CONFIG_BOOTCOMMAND                                              \
  35         "if fatload mmc 0 0xa0000000 uImage; then "                     \
  36                 "bootm 0xa0000000; "                                    \
  37         "fi; "                                                          \
  38         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
  39                 "bootm 0xa0000000; "                                    \
  40         "fi; "                                                          \
  41         "bootm 0xc0000;"
  42 #define CONFIG_TIMESTAMP
  43 #define CONFIG_CMDLINE_TAG
  44 #define CONFIG_SETUP_MEMORY_TAGS
  45
  46 /*
  47  * Serial Console Configuration
  48  */
  49
  50 /*
  51  * Bootloader Components Configuration
  52  */
  53
  54 /* I2C support */
  55 #ifdef CONFIG_SYS_I2C
  56 #define CONFIG_SYS_I2C_PXA
  57 #define CONFIG_PXA_STD_I2C
  58 #define CONFIG_PXA_PWR_I2C
  59 #define CONFIG_SYS_I2C_SPEED            100000
  60 #endif
  61
  62 /* LCD support */
  63 #ifdef CONFIG_LCD
  64 #define CONFIG_PXA_LCD
  65 #define CONFIG_PXA_VGA
  66 #define CONFIG_LCD_LOGO
  67 #endif
  68
  69 /*
  70  * Networking Configuration
  71  */
  72 #ifdef  CONFIG_CMD_NET
  73
  74 #define CONFIG_DRIVER_DM9000            1
  75 #define CONFIG_DM9000_BASE              0x08000000
  76 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  77 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  78 #define CONFIG_NET_RETRY_COUNT          10
  79
  80 #define CONFIG_BOOTP_BOOTFILESIZE
  81 #define CONFIG_BOOTP_BOOTPATH
  82 #define CONFIG_BOOTP_GATEWAY
  83 #define CONFIG_BOOTP_HOSTNAME
  84 #endif
  85
  86 #undef  CONFIG_SYS_LONGHELP             /* Saves 10 KB */
  87 #define CONFIG_SYS_DEVICE_NULLDEV       1
  88 #undef  CONFIG_CMDLINE_EDITING          /* Saves 2.5 KB */
  89 #undef  CONFIG_AUTO_COMPLETE            /* Saves 2.5 KB */
  90
  91 /*
  92  * Clock Configuration
  93  */
  94 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  95
  96 /*
  97  * DRAM Map
  98  */
  99 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
 100 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 101 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
 102
 103 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 104 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
 105
 106 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 107 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 108
 109 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
 110 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 111 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
 112
 113 /*
 114  * NOR FLASH
 115  */
 116 #ifdef  CONFIG_CMD_FLASH
 117 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 118 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
 119 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 120
 121 #define CONFIG_SYS_FLASH_CFI
 122 #define CONFIG_FLASH_CFI_DRIVER         1
 123 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
 124
 125 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
 126 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 127
 128 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
 129 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
 130 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
 131 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
 132
 133 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 134 #define CONFIG_SYS_FLASH_PROTECTION             1
 135 #endif
 136
 137 #define CONFIG_SYS_MONITOR_BASE         0x0
 138 #define CONFIG_SYS_MONITOR_LEN          0x40000
 139
 140 /* Skip factory configuration block */
 141 #define CONFIG_ENV_ADDR                 \
 142                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
 143 #define CONFIG_ENV_SIZE                 0x40000
 144 #define CONFIG_ENV_SECT_SIZE            0x40000
 145
 146 /*
 147  * GPIO settings
 148  */
 149 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 150 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 151 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
 152 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 153
 154 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 155 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 156 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 157 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 158
 159 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 160 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 161 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 162 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 163
 164 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 165 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 166 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 167 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 168 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 169 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 170 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 171 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 172
 173 #define CONFIG_SYS_PSSR_VAL     0x30
 174
 175 /*
 176  * Clock settings
 177  */
 178 #define CONFIG_SYS_CKEN         0x00500240
 179 #define CONFIG_SYS_CCCR         0x02000290
 180
 181 /*
 182  * Memory settings
 183  */
 184 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 185 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 186 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 187 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 188 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 189 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 190 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 191 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 192
 193 /*
 194  * PCMCIA and CF Interfaces
 195  */
 196 #define CONFIG_SYS_MECR_VAL     0x00000000
 197 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 198 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 199 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 200 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 201 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 202 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 203
 204 #include "pxa-common.h"
 205
 206 #endif /* __CONFIG_H */