include/configs/colibri_pxa270.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Toradex Colibri PXA270 configuration file
   4  *
   5  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   6  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Board Configuration Options
  14  */
  15 /* Avoid overwriting factory configuration block */
  16 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  17
  18 /*
  19  * Environment settings
  20  */
  21 #define CONFIG_TIMESTAMP
  22
  23 /*
  24  * Serial Console Configuration
  25  */
  26
  27 /*
  28  * Bootloader Components Configuration
  29  */
  30
  31 /* I2C support */
  32 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
  33 #define CONFIG_SYS_I2C_PXA
  34 #define CONFIG_PXA_STD_I2C
  35 #define CONFIG_PXA_PWR_I2C
  36 #endif
  37
  38 /* LCD support */
  39 #ifdef CONFIG_LCD
  40 #define CONFIG_PXA_LCD
  41 #define CONFIG_PXA_VGA
  42 #define CONFIG_LCD_LOGO
  43 #endif
  44
  45 /*
  46  * Networking Configuration
  47  */
  48 #ifdef  CONFIG_CMD_NET
  49
  50 #define CONFIG_DRIVER_DM9000            1
  51 #define CONFIG_DM9000_BASE              0x08000000
  52 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  53 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  54 #define CONFIG_NET_RETRY_COUNT          10
  55
  56 #define CONFIG_BOOTP_BOOTFILESIZE
  57 #endif
  58
  59 /*
  60  * Clock Configuration
  61  */
  62 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  63
  64 /*
  65  * DRAM Map
  66  */
  67 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
  68 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
  69
  70 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
  71 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
  72
  73 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  74 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
  75
  76 /*
  77  * NOR FLASH
  78  */
  79 #ifdef  CONFIG_CMD_FLASH
  80 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
  81 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
  82 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
  83
  84 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
  85
  86 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
  87 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  88
  89 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
  90 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
  91 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
  92 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
  93 #endif
  94
  95 #define CONFIG_SYS_MONITOR_BASE         0x0
  96 #define CONFIG_SYS_MONITOR_LEN          0x40000
  97
  98 /* Skip factory configuration block */
  99
 100 /*
 101  * GPIO settings
 102  */
 103 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 104 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 105 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
 106 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 107
 108 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 109 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 110 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 111 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 112
 113 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 114 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 115 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 116 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 117
 118 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 119 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 120 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 121 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 122 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 123 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 124 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 125 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 126
 127 #define CONFIG_SYS_PSSR_VAL     0x30
 128
 129 /*
 130  * Clock settings
 131  */
 132 #define CONFIG_SYS_CKEN         0x00500240
 133 #define CONFIG_SYS_CCCR         0x02000290
 134
 135 /*
 136  * Memory settings
 137  */
 138 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 139 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 140 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 141 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 142 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 143 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 144 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 145 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 146
 147 /*
 148  * PCMCIA and CF Interfaces
 149  */
 150 #define CONFIG_SYS_MECR_VAL     0x00000000
 151 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 152 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 153 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 154 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 155 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 156 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 157
 158 #include "pxa-common.h"
 159
 160 #endif /* __CONFIG_H */