2 * Toradex Colibri PXA270 configuration file
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5 * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 * High Level Board Configuration Options
16 #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
17 #define CONFIG_SYS_GENERIC_BOARD
18 #define CONFIG_SYS_TEXT_BASE 0x0
19 /* Avoid overwriting factory configuration block */
20 #define CONFIG_BOARD_SIZE_LIMIT 0x40000
22 /* We will never enable dcache because we have to setup MMU first */
23 #define CONFIG_SYS_DCACHE_OFF
26 * Environment settings
28 #define CONFIG_ENV_OVERWRITE
29 #define CONFIG_SYS_MALLOC_LEN (128 * 1024)
30 #define CONFIG_ARCH_CPU_INIT
31 #define CONFIG_BOOTCOMMAND \
32 "if fatload mmc 0 0xa0000000 uImage; then " \
33 "bootm 0xa0000000; " \
35 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
36 "bootm 0xa0000000; " \
39 #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
40 #define CONFIG_TIMESTAMP
41 #define CONFIG_BOOTDELAY 2 /* Autoboot delay */
42 #define CONFIG_CMDLINE_TAG
43 #define CONFIG_SETUP_MEMORY_TAGS
44 #define CONFIG_LZMA /* LZMA compression support */
45 #define CONFIG_OF_LIBFDT
48 * Serial Console Configuration
50 #define CONFIG_PXA_SERIAL
51 #define CONFIG_FFUART 1
52 #define CONFIG_CONS_INDEX 3
53 #define CONFIG_BAUDRATE 115200
56 * Bootloader Components Configuration
58 #define CONFIG_CMD_ENV
59 #define CONFIG_CMD_MMC
60 #define CONFIG_CMD_USB
64 #define CONFIG_PXA_LCD
65 #define CONFIG_PXA_VGA
66 #define CONFIG_SYS_WHITE_ON_BLACK
67 #define CONFIG_CONSOLE_SCROLL_LINES 10
68 #define CONFIG_CMD_BMP
69 #define CONFIG_LCD_LOGO
73 * Networking Configuration
76 #define CONFIG_CMD_PING
77 #define CONFIG_CMD_DHCP
79 #define CONFIG_DRIVER_DM9000 1
80 #define CONFIG_DM9000_BASE 0x08000000
81 #define DM9000_IO (CONFIG_DM9000_BASE)
82 #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
83 #define CONFIG_NET_RETRY_COUNT 10
85 #define CONFIG_BOOTP_BOOTFILESIZE
86 #define CONFIG_BOOTP_BOOTPATH
87 #define CONFIG_BOOTP_GATEWAY
88 #define CONFIG_BOOTP_HOSTNAME
92 * HUSH Shell Configuration
94 #define CONFIG_SYS_HUSH_PARSER 1
96 #undef CONFIG_SYS_LONGHELP /* Saves 10 KB */
97 #undef CONFIG_SYS_PROMPT
98 #ifdef CONFIG_SYS_HUSH_PARSER
99 #define CONFIG_SYS_PROMPT "$ "
102 #define CONFIG_SYS_CBSIZE 256
103 #define CONFIG_SYS_PBSIZE \
104 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
105 #define CONFIG_SYS_MAXARGS 16
106 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
107 #define CONFIG_SYS_DEVICE_NULLDEV 1
108 #define CONFIG_CMDLINE_EDITING 1
109 #define CONFIG_AUTO_COMPLETE 1
112 * Clock Configuration
114 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
119 #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
120 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
121 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
123 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
124 #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
126 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
127 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
129 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
130 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
131 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
136 #ifdef CONFIG_CMD_FLASH
137 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
138 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
139 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
141 #define CONFIG_SYS_FLASH_CFI
142 #define CONFIG_FLASH_CFI_DRIVER 1
143 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
145 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
146 #define CONFIG_SYS_MAX_FLASH_BANKS 1
148 #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
149 #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
150 #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
151 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
153 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
154 #define CONFIG_SYS_FLASH_PROTECTION 1
156 #define CONFIG_ENV_IS_IN_FLASH 1
159 #define CONFIG_SYS_NO_FLASH
160 #define CONFIG_ENV_IS_NOWHERE
163 #define CONFIG_SYS_MONITOR_BASE 0x0
164 #define CONFIG_SYS_MONITOR_LEN 0x40000
166 /* Skip factory configuration block */
167 #define CONFIG_ENV_ADDR \
168 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
169 #define CONFIG_ENV_SIZE 0x40000
170 #define CONFIG_ENV_SECT_SIZE 0x40000
175 #define CONFIG_SYS_GPSR0_VAL 0x00000000
176 #define CONFIG_SYS_GPSR1_VAL 0x00020000
177 #define CONFIG_SYS_GPSR2_VAL 0x0002c000
178 #define CONFIG_SYS_GPSR3_VAL 0x00000000
180 #define CONFIG_SYS_GPCR0_VAL 0x00000000
181 #define CONFIG_SYS_GPCR1_VAL 0x00000000
182 #define CONFIG_SYS_GPCR2_VAL 0x00000000
183 #define CONFIG_SYS_GPCR3_VAL 0x00000000
185 #define CONFIG_SYS_GPDR0_VAL 0xc8008000
186 #define CONFIG_SYS_GPDR1_VAL 0xfc02a981
187 #define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
188 #define CONFIG_SYS_GPDR3_VAL 0x0061e804
190 #define CONFIG_SYS_GAFR0_L_VAL 0x80100000
191 #define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
192 #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
193 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
194 #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
195 #define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
196 #define CONFIG_SYS_GAFR3_L_VAL 0x54000310
197 #define CONFIG_SYS_GAFR3_U_VAL 0x00005401
199 #define CONFIG_SYS_PSSR_VAL 0x30
204 #define CONFIG_SYS_CKEN 0x00500240
205 #define CONFIG_SYS_CCCR 0x02000290
210 #define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
211 #define CONFIG_SYS_MSC1_VAL 0x9ee1f994
212 #define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
213 #define CONFIG_SYS_MDCNFG_VAL 0x090009c9
214 #define CONFIG_SYS_MDREFR_VAL 0x2003a031
215 #define CONFIG_SYS_MDMRS_VAL 0x00220022
216 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001
217 #define CONFIG_SYS_SXCNFG_VAL 0x40044004
220 * PCMCIA and CF Interfaces
222 #define CONFIG_SYS_MECR_VAL 0x00000000
223 #define CONFIG_SYS_MCMEM0_VAL 0x00028307
224 #define CONFIG_SYS_MCMEM1_VAL 0x00014307
225 #define CONFIG_SYS_MCATT0_VAL 0x00038787
226 #define CONFIG_SYS_MCATT1_VAL 0x0001c787
227 #define CONFIG_SYS_MCIO0_VAL 0x0002830f
228 #define CONFIG_SYS_MCIO1_VAL 0x0001430f
230 #include "pxa-common.h"
232 #endif /* __CONFIG_H */