include/configs/colibri_pxa270.h

   1 /*
   2  * Toradex Colibri PXA270 configuration file
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  * Copyright (C) 2015 Marcel Ziswiler <marcel@ziswiler.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Board Configuration Options
  15  */
  16 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  17 #define CONFIG_SYS_GENERIC_BOARD
  18 #define CONFIG_SYS_TEXT_BASE            0x0
  19 /* Avoid overwriting factory configuration block */
  20 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  21
  22 /*
  23  * Environment settings
  24  */
  25 #define CONFIG_ENV_OVERWRITE
  26 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)
  27 #define CONFIG_ARCH_CPU_INIT
  28 #define CONFIG_BOOTCOMMAND                                              \
  29         "if fatload mmc 0 0xa0000000 uImage; then "                     \
  30                 "bootm 0xa0000000; "                                    \
  31         "fi; "                                                          \
  32         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
  33                 "bootm 0xa0000000; "                                    \
  34         "fi; "                                                          \
  35         "bootm 0xc0000;"
  36 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,115200"
  37 #define CONFIG_TIMESTAMP
  38 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
  39 #define CONFIG_CMDLINE_TAG
  40 #define CONFIG_SETUP_MEMORY_TAGS
  41 #define CONFIG_LZMA                     /* LZMA compression support */
  42 #define CONFIG_OF_LIBFDT
  43
  44 /*
  45  * Serial Console Configuration
  46  */
  47 #define CONFIG_PXA_SERIAL
  48 #define CONFIG_FFUART                   1
  49 #define CONFIG_CONS_INDEX               3
  50 #define CONFIG_BAUDRATE                 115200
  51
  52 /*
  53  * Bootloader Components Configuration
  54  */
  55 #define CONFIG_CMD_ENV
  56 #define CONFIG_CMD_MMC
  57 #define CONFIG_CMD_USB
  58
  59 /*
  60  * Networking Configuration
  61  */
  62 #ifdef  CONFIG_CMD_NET
  63 #define CONFIG_CMD_PING
  64 #define CONFIG_CMD_DHCP
  65
  66 #define CONFIG_DRIVER_DM9000            1
  67 #define CONFIG_DM9000_BASE              0x08000000
  68 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  69 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  70 #define CONFIG_NET_RETRY_COUNT          10
  71
  72 #define CONFIG_BOOTP_BOOTFILESIZE
  73 #define CONFIG_BOOTP_BOOTPATH
  74 #define CONFIG_BOOTP_GATEWAY
  75 #define CONFIG_BOOTP_HOSTNAME
  76 #endif
  77
  78 /*
  79  * HUSH Shell Configuration
  80  */
  81 #define CONFIG_SYS_HUSH_PARSER          1
  82
  83 #undef  CONFIG_SYS_LONGHELP             /* Saves 10 KB */
  84 #ifdef  CONFIG_SYS_HUSH_PARSER
  85 #define CONFIG_SYS_PROMPT               "$ "
  86 #else
  87 #endif
  88 #define CONFIG_SYS_CBSIZE               256
  89 #define CONFIG_SYS_PBSIZE               \
  90         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  91 #define CONFIG_SYS_MAXARGS              16
  92 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  93 #define CONFIG_SYS_DEVICE_NULLDEV       1
  94 #define CONFIG_CMDLINE_EDITING          1
  95 #define CONFIG_AUTO_COMPLETE            1
  96
  97 /*
  98  * Clock Configuration
  99  */
 100 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
 101
 102 /*
 103  * DRAM Map
 104  */
 105 #define CONFIG_NR_DRAM_BANKS            1               /* We have 1 bank of DRAM */
 106 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 107 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
 108
 109 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 110 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
 111
 112 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 113 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 114
 115 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
 116 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 117 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
 118
 119 /*
 120  * NOR FLASH
 121  */
 122 #ifdef  CONFIG_CMD_FLASH
 123 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 124 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 125
 126 #define CONFIG_SYS_FLASH_CFI
 127 #define CONFIG_FLASH_CFI_DRIVER         1
 128
 129 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
 130 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 131
 132 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
 133 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
 134
 135 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 136 #define CONFIG_SYS_FLASH_PROTECTION             1
 137
 138 #define CONFIG_ENV_IS_IN_FLASH          1
 139
 140 #else   /* No flash */
 141 #define CONFIG_SYS_NO_FLASH
 142 #define CONFIG_ENV_IS_NOWHERE
 143 #endif
 144
 145 #define CONFIG_SYS_MONITOR_BASE         0x0
 146 #define CONFIG_SYS_MONITOR_LEN          0x40000
 147
 148 /* Skip factory configuration block */
 149 #define CONFIG_ENV_ADDR                 \
 150                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
 151 #define CONFIG_ENV_SIZE                 0x40000
 152 #define CONFIG_ENV_SECT_SIZE            0x40000
 153
 154 /*
 155  * GPIO settings
 156  */
 157 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 158 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 159 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
 160 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 161
 162 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 163 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 164 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 165 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 166
 167 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 168 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 169 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 170 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 171
 172 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 173 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 174 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 175 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 176 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 177 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 178 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 179 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 180
 181 #define CONFIG_SYS_PSSR_VAL     0x30
 182
 183 /*
 184  * Clock settings
 185  */
 186 #define CONFIG_SYS_CKEN         0x00500240
 187 #define CONFIG_SYS_CCCR         0x02000290
 188
 189 /*
 190  * Memory settings
 191  */
 192 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 193 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 194 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 195 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 196 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 197 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 198 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 199 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 200
 201 /*
 202  * PCMCIA and CF Interfaces
 203  */
 204 #define CONFIG_SYS_MECR_VAL     0x00000000
 205 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 206 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 207 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 208 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 209 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 210 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 211
 212 #include "pxa-common.h"
 213
 214 #endif /* __CONFIG_H */