1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Toradex Colibri PXA270 configuration file
5 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6 * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
13 * High Level Board Configuration Options
17 * Environment settings
21 * Serial Console Configuration
25 * Bootloader Components Configuration
29 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
30 #define CONFIG_SYS_I2C_PXA
31 #define CONFIG_PXA_STD_I2C
32 #define CONFIG_PXA_PWR_I2C
37 #define CONFIG_PXA_LCD
38 #define CONFIG_PXA_VGA
42 * Networking Configuration
46 #define CONFIG_DM9000_BASE 0x08000000
47 #define DM9000_IO (CONFIG_DM9000_BASE)
48 #define DM9000_DATA (CONFIG_DM9000_BASE + 4)
54 #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
59 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
60 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
62 #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
63 #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
65 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
66 #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
71 #ifdef CONFIG_CMD_FLASH
72 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
73 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
74 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
76 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
78 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
80 #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
81 #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
82 #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
83 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
86 #define CONFIG_SYS_MONITOR_LEN 0x40000
88 /* Skip factory configuration block */
93 #define CONFIG_SYS_GPSR0_VAL 0x00000000
94 #define CONFIG_SYS_GPSR1_VAL 0x00020000
95 #define CONFIG_SYS_GPSR2_VAL 0x0002c000
96 #define CONFIG_SYS_GPSR3_VAL 0x00000000
98 #define CONFIG_SYS_GPCR0_VAL 0x00000000
99 #define CONFIG_SYS_GPCR1_VAL 0x00000000
100 #define CONFIG_SYS_GPCR2_VAL 0x00000000
101 #define CONFIG_SYS_GPCR3_VAL 0x00000000
103 #define CONFIG_SYS_GPDR0_VAL 0xc8008000
104 #define CONFIG_SYS_GPDR1_VAL 0xfc02a981
105 #define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
106 #define CONFIG_SYS_GPDR3_VAL 0x0061e804
108 #define CONFIG_SYS_GAFR0_L_VAL 0x80100000
109 #define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
110 #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
111 #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
112 #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
113 #define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
114 #define CONFIG_SYS_GAFR3_L_VAL 0x54000310
115 #define CONFIG_SYS_GAFR3_U_VAL 0x00005401
117 #define CONFIG_SYS_PSSR_VAL 0x30
122 #define CONFIG_SYS_CKEN 0x00500240
123 #define CONFIG_SYS_CCCR 0x02000290
128 #define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
129 #define CONFIG_SYS_MSC1_VAL 0x9ee1f994
130 #define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
131 #define CONFIG_SYS_MDCNFG_VAL 0x090009c9
132 #define CONFIG_SYS_MDREFR_VAL 0x2003a031
133 #define CONFIG_SYS_MDMRS_VAL 0x00220022
134 #define CONFIG_SYS_FLYCNFG_VAL 0x00010001
135 #define CONFIG_SYS_SXCNFG_VAL 0x40044004
138 * PCMCIA and CF Interfaces
140 #define CONFIG_SYS_MECR_VAL 0x00000000
141 #define CONFIG_SYS_MCMEM0_VAL 0x00028307
142 #define CONFIG_SYS_MCMEM1_VAL 0x00014307
143 #define CONFIG_SYS_MCATT0_VAL 0x00038787
144 #define CONFIG_SYS_MCATT1_VAL 0x0001c787
145 #define CONFIG_SYS_MCIO0_VAL 0x0002830f
146 #define CONFIG_SYS_MCIO1_VAL 0x0001430f
148 #include "pxa-common.h"
150 #endif /* __CONFIG_H */