include/configs/colibri_pxa270.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Toradex Colibri PXA270 configuration file
   4  *
   5  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   6  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Board Configuration Options
  14  */
  15 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  16 /* Avoid overwriting factory configuration block */
  17 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  18
  19 /*
  20  * Environment settings
  21  */
  22 #define CONFIG_TIMESTAMP
  23
  24 /*
  25  * Serial Console Configuration
  26  */
  27
  28 /*
  29  * Bootloader Components Configuration
  30  */
  31
  32 /* I2C support */
  33 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
  34 #define CONFIG_SYS_I2C_PXA
  35 #define CONFIG_PXA_STD_I2C
  36 #define CONFIG_PXA_PWR_I2C
  37 #endif
  38
  39 /* LCD support */
  40 #ifdef CONFIG_LCD
  41 #define CONFIG_PXA_LCD
  42 #define CONFIG_PXA_VGA
  43 #define CONFIG_LCD_LOGO
  44 #endif
  45
  46 /*
  47  * Networking Configuration
  48  */
  49 #ifdef  CONFIG_CMD_NET
  50
  51 #define CONFIG_DRIVER_DM9000            1
  52 #define CONFIG_DM9000_BASE              0x08000000
  53 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  54 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  55 #define CONFIG_NET_RETRY_COUNT          10
  56
  57 #define CONFIG_BOOTP_BOOTFILESIZE
  58 #endif
  59
  60 /*
  61  * Clock Configuration
  62  */
  63 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  64
  65 /*
  66  * DRAM Map
  67  */
  68 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
  69 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
  70
  71 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
  72 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
  73
  74 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  75 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
  76
  77 /*
  78  * NOR FLASH
  79  */
  80 #ifdef  CONFIG_CMD_FLASH
  81 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
  82 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
  83 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
  84
  85 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
  86
  87 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
  88 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  89
  90 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
  91 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
  92 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
  93 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
  94 #endif
  95
  96 #define CONFIG_SYS_MONITOR_BASE         0x0
  97 #define CONFIG_SYS_MONITOR_LEN          0x40000
  98
  99 /* Skip factory configuration block */
 100
 101 /*
 102  * GPIO settings
 103  */
 104 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 105 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 106 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
 107 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 108
 109 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 110 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 111 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 112 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 113
 114 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 115 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 116 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 117 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 118
 119 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 120 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 121 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 122 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 123 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 124 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 125 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 126 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 127
 128 #define CONFIG_SYS_PSSR_VAL     0x30
 129
 130 /*
 131  * Clock settings
 132  */
 133 #define CONFIG_SYS_CKEN         0x00500240
 134 #define CONFIG_SYS_CCCR         0x02000290
 135
 136 /*
 137  * Memory settings
 138  */
 139 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 140 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 141 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 142 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 143 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 144 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 145 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 146 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 147
 148 /*
 149  * PCMCIA and CF Interfaces
 150  */
 151 #define CONFIG_SYS_MECR_VAL     0x00000000
 152 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 153 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 154 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 155 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 156 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 157 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 158
 159 #include "pxa-common.h"
 160
 161 #endif /* __CONFIG_H */