include/configs/colibri_pxa270.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Toradex Colibri PXA270 configuration file
   4  *
   5  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   6  * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Board Configuration Options
  14  */
  15 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  16 /* Avoid overwriting factory configuration block */
  17 #define CONFIG_BOARD_SIZE_LIMIT         0x40000
  18
  19 /*
  20  * Environment settings
  21  */
  22 #define CONFIG_BOOTCOMMAND                                              \
  23         "if fatload mmc 0 0xa0000000 uImage; then "                     \
  24                 "bootm 0xa0000000; "                                    \
  25         "fi; "                                                          \
  26         "if usb reset && fatload usb 0 0xa0000000 uImage; then "        \
  27                 "bootm 0xa0000000; "                                    \
  28         "fi; "                                                          \
  29         "bootm 0xc0000;"
  30 #define CONFIG_TIMESTAMP
  31
  32 /*
  33  * Serial Console Configuration
  34  */
  35
  36 /*
  37  * Bootloader Components Configuration
  38  */
  39
  40 /* I2C support */
  41 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
  42 #define CONFIG_SYS_I2C_PXA
  43 #define CONFIG_PXA_STD_I2C
  44 #define CONFIG_PXA_PWR_I2C
  45 #endif
  46
  47 /* LCD support */
  48 #ifdef CONFIG_LCD
  49 #define CONFIG_PXA_LCD
  50 #define CONFIG_PXA_VGA
  51 #define CONFIG_LCD_LOGO
  52 #endif
  53
  54 /*
  55  * Networking Configuration
  56  */
  57 #ifdef  CONFIG_CMD_NET
  58
  59 #define CONFIG_DRIVER_DM9000            1
  60 #define CONFIG_DM9000_BASE              0x08000000
  61 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  62 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  63 #define CONFIG_NET_RETRY_COUNT          10
  64
  65 #define CONFIG_BOOTP_BOOTFILESIZE
  66 #endif
  67
  68 /*
  69  * Clock Configuration
  70  */
  71 #define CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
  72
  73 /*
  74  * DRAM Map
  75  */
  76 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
  77 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
  78
  79 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
  80 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
  81
  82 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  83 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
  84
  85 /*
  86  * NOR FLASH
  87  */
  88 #ifdef  CONFIG_CMD_FLASH
  89 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
  90 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
  91 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
  92
  93 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
  94
  95 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
  96 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  97
  98 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25 * CONFIG_SYS_HZ)
  99 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25 * CONFIG_SYS_HZ)
 100 #define CONFIG_SYS_FLASH_LOCK_TOUT      (25 * CONFIG_SYS_HZ)
 101 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (25 * CONFIG_SYS_HZ)
 102 #endif
 103
 104 #define CONFIG_SYS_MONITOR_BASE         0x0
 105 #define CONFIG_SYS_MONITOR_LEN          0x40000
 106
 107 /* Skip factory configuration block */
 108
 109 /*
 110  * GPIO settings
 111  */
 112 #define CONFIG_SYS_GPSR0_VAL    0x00000000
 113 #define CONFIG_SYS_GPSR1_VAL    0x00020000
 114 #define CONFIG_SYS_GPSR2_VAL    0x0002c000
 115 #define CONFIG_SYS_GPSR3_VAL    0x00000000
 116
 117 #define CONFIG_SYS_GPCR0_VAL    0x00000000
 118 #define CONFIG_SYS_GPCR1_VAL    0x00000000
 119 #define CONFIG_SYS_GPCR2_VAL    0x00000000
 120 #define CONFIG_SYS_GPCR3_VAL    0x00000000
 121
 122 #define CONFIG_SYS_GPDR0_VAL    0xc8008000
 123 #define CONFIG_SYS_GPDR1_VAL    0xfc02a981
 124 #define CONFIG_SYS_GPDR2_VAL    0x92c3ffff
 125 #define CONFIG_SYS_GPDR3_VAL    0x0061e804
 126
 127 #define CONFIG_SYS_GAFR0_L_VAL  0x80100000
 128 #define CONFIG_SYS_GAFR0_U_VAL  0xa5c00010
 129 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 130 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa50008
 131 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 132 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a002
 133 #define CONFIG_SYS_GAFR3_L_VAL  0x54000310
 134 #define CONFIG_SYS_GAFR3_U_VAL  0x00005401
 135
 136 #define CONFIG_SYS_PSSR_VAL     0x30
 137
 138 /*
 139  * Clock settings
 140  */
 141 #define CONFIG_SYS_CKEN         0x00500240
 142 #define CONFIG_SYS_CCCR         0x02000290
 143
 144 /*
 145  * Memory settings
 146  */
 147 #define CONFIG_SYS_MSC0_VAL     0x9ee1c5f2
 148 #define CONFIG_SYS_MSC1_VAL     0x9ee1f994
 149 #define CONFIG_SYS_MSC2_VAL     0x9ee19ee1
 150 #define CONFIG_SYS_MDCNFG_VAL   0x090009c9
 151 #define CONFIG_SYS_MDREFR_VAL   0x2003a031
 152 #define CONFIG_SYS_MDMRS_VAL    0x00220022
 153 #define CONFIG_SYS_FLYCNFG_VAL  0x00010001
 154 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 155
 156 /*
 157  * PCMCIA and CF Interfaces
 158  */
 159 #define CONFIG_SYS_MECR_VAL     0x00000000
 160 #define CONFIG_SYS_MCMEM0_VAL   0x00028307
 161 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 162 #define CONFIG_SYS_MCATT0_VAL   0x00038787
 163 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 164 #define CONFIG_SYS_MCIO0_VAL    0x0002830f
 165 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 166
 167 #include "pxa-common.h"
 168
 169 #endif /* __CONFIG_H */