3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Config header file for Cogent platform using an MPC8xx CPU module
32 * High Level Configuration Options
36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37 #define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
39 /* Cogent Modular Architecture options */
40 #define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */
41 #define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */
44 * select serial console configuration
46 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
47 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
50 * if CONFIG_CONS_NONE is defined, then the serial console routines must
51 * defined elsewhere (for example, on the cogent platform, there are serial
52 * ports on the motherboard which are used for the serial console - see
53 * cogent/cma101/serial.[ch]).
55 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
56 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
57 #undef CONFIG_CONS_NONE /* define if console on something else*/
58 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
59 #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
60 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
61 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
64 * select ethernet configuration
66 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
67 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
70 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
71 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
72 * from CONFIG_COMMANDS to remove support for networking.
74 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
75 #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
76 #define CONFIG_ETHER_NONE /* define if ether on something else */
77 #define CONFIG_ETHER_INDEX 1 /* which channel for ether */
79 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
80 #define CONFIG_8260_CLKIN 66666666 /* in Hz */
82 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
83 #define CONFIG_BAUDRATE 230400
85 #define CONFIG_BAUDRATE 9600
88 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET)
90 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
91 #include <cmd_confdefs.h>
94 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
96 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
98 #define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
100 #define CONFIG_BOOTARGS "root=/dev/ram rw"
102 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
103 #define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
104 #undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
105 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
106 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
107 #define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
108 #define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
109 #define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
110 # if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
111 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */
113 #define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
117 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
120 * Miscellaneous configurable options
122 #define CFG_LONGHELP /* undef to save memory */
123 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
124 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
125 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
127 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
129 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
130 #define CFG_MAXARGS 16 /* max number of command args */
131 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
133 #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
134 #define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
136 #define CFG_LOAD_ADDR 0x100000 /* default load address */
138 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
140 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
143 * Low Level Configuration Settings
144 * (address mappings, register initial values, etc.)
145 * You should know what you are doing if you make changes here.
148 /*-----------------------------------------------------------------------
149 * Low Level Cogent settings
150 * if CFG_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
151 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
152 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
153 * (second 2 for CMA120 only)
155 #define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */
157 #include <configs/cogent_common.h>
159 #ifdef CONFIG_CONS_NONE
160 #define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
162 #define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
163 #define CONFIG_SHOW_ACTIVITY
165 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
167 * flash exists on the motherboard
168 * set these four according to TOP dipsw:
169 * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
170 * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
172 #define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
173 #define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
174 #define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
175 #define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
177 #define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
178 #define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
180 /*-----------------------------------------------------------------------
181 * Hard Reset Configuration Words
183 * if you change bits in the HRCW, you must also change the CFG_*
184 * defines for the various registers affected by the HRCW e.g. changing
185 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
187 #define CFG_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
188 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
189 /* no slaves so just duplicate the master hrcw */
190 #define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
191 #define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
192 #define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
193 #define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
194 #define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
195 #define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
196 #define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
198 /*-----------------------------------------------------------------------
199 * Internal Memory Mapped Register
201 #define CFG_IMMR 0xF0000000
203 /*-----------------------------------------------------------------------
204 * Definitions for initial stack pointer and data area (in DPRAM)
206 #define CFG_INIT_RAM_ADDR CFG_IMMR
207 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
208 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
209 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
210 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
212 /*-----------------------------------------------------------------------
213 * Start addresses for the final memory configuration
214 * (Set up by the startup code)
215 * Please note that CFG_SDRAM_BASE _must_ start at 0
217 #define CFG_SDRAM_BASE CMA_MB_RAM_BASE
219 #define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
221 #define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
223 #define CFG_MONITOR_BASE TEXT_BASE
224 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
225 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
228 * For booting Linux, the board info and command line data
229 * have to be in the first 8 MB of memory, since this is
230 * the maximum mapped by the Linux kernel during initialization.
232 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
234 /*-----------------------------------------------------------------------
237 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
238 #define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
240 #define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
241 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
243 #define CFG_ENV_IS_IN_FLASH 1
244 #define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
246 #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
247 #define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
249 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
252 /*-----------------------------------------------------------------------
253 * Cache Configuration
255 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
256 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
257 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
260 /*-----------------------------------------------------------------------
261 * HIDx - Hardware Implementation-dependent Registers 2-11
262 *-----------------------------------------------------------------------
263 * HID0 also contains cache control - initially enable both caches and
264 * invalidate contents, then the final state leaves only the instruction
265 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
266 * but Soft reset does not.
268 * HID1 has only read-only information - nothing to set.
270 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
272 #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
275 /*-----------------------------------------------------------------------
276 * RMR - Reset Mode Register 5-5
277 *-----------------------------------------------------------------------
278 * turn on Checkstop Reset Enable
280 #define CFG_RMR RMR_CSRE
282 /*-----------------------------------------------------------------------
283 * BCR - Bus Configuration 4-25
284 *-----------------------------------------------------------------------
286 #define CFG_BCR BCR_EBM
288 /*-----------------------------------------------------------------------
289 * SIUMCR - SIU Module Configuration 4-31
290 *-----------------------------------------------------------------------
292 #define CFG_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
294 /*-----------------------------------------------------------------------
295 * SYPCR - System Protection Control 4-35
296 * SYPCR can only be written once after reset!
297 *-----------------------------------------------------------------------
298 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
300 #if defined(CONFIG_WATCHDOG)
301 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
302 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
304 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
305 SYPCR_SWRI|SYPCR_SWP)
306 #endif /* CONFIG_WATCHDOG */
308 /*-----------------------------------------------------------------------
309 * TMCNTSC - Time Counter Status and Control 4-40
310 *-----------------------------------------------------------------------
311 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
312 * and enable Time Counter
314 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
316 /*-----------------------------------------------------------------------
317 * PISCR - Periodic Interrupt Status and Control 4-42
318 *-----------------------------------------------------------------------
319 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
322 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
324 /*-----------------------------------------------------------------------
325 * SCCR - System Clock Control 9-8
326 *-----------------------------------------------------------------------
327 * Ensure DFBRG is Divide by 16
329 #define CFG_SCCR (SCCR_DFBRG01)
331 /*-----------------------------------------------------------------------
332 * RCCR - RISC Controller Configuration 13-7
333 *-----------------------------------------------------------------------
337 #if defined(CONFIG_CMA282)
340 * Init Memory Controller:
342 * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
343 * and CS2 for (optional) local bus RAM on the CPU module.
345 * Note the motherboard address space (256 Mbyte in size) is connected
346 * to the 60x Bus and is located starting at address 0. The Hard Reset
347 * Configuration Word should put the 60x Bus into External Bus Mode, since
348 * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
350 * (the *_SIZE vars must be a power of 2)
353 #define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */
354 #define CFG_CMA_CS0_SIZE (1 << 20)
356 #define CFG_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */
357 #define CFG_CMA_CS2_SIZE (16 << 20)
361 * CS0 maps the EPROM on the cpu module
362 * Set it for 10 wait states, address CFG_MONITOR_BASE and size 1M
364 * Note: We must have already transferred control to the final location
365 * of the EPROM before these are used, because when BR0/OR0 are set, the
366 * mirror of the eprom at any other addresses will disappear.
369 /* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
370 #define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
371 /* mask size CFG_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
372 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_CMA_CS0_SIZE)|\
373 ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
376 * CS2 enables the Local Bus SDRAM on the CPU Module
378 * Will leave this unset for the moment, because a) my CPU module has no
379 * SDRAM installed (it is optional); and b) it will require programming
380 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
381 * if you can't test it.
385 /* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, ??? */
386 #define CFG_BR0_PRELIM ((CFG_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
387 /* mask size CFG_CMA_CS2_SIZE, CS time normal, ??? */
388 #define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
394 * Internal Definitions
398 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
399 #define BOOTFLAG_WARM 0x02 /* Software reboot */
401 #endif /* __CONFIG_H */