include/configs/cmpcpro.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006-2023  CS GROUP France
   4  */
   5
   6 #ifndef __CONFIG_H
   7 #define __CONFIG_H
   8
   9 #include <linux/sizes.h>
  10
  11 /*
  12  * System IO Config
  13  */
  14 #define CFG_SYS_SICRL           0x00000000
  15
  16 #define CFG_SYS_DDR_SDRAM_BASE  0x00000000
  17
  18 #define CFG_SYS_DDRCDR          0x73000002      /* DDR II voltage is 1.8V */
  19
  20 /*
  21  * Manually set up DDR parameters
  22  */
  23
  24 /* DDR 512 M */
  25 #define CFG_SYS_DDR_CS0_CONFIG  (CSCONFIG_EN | CSCONFIG_ODT_WR_CFG | CSCONFIG_BANK_BIT_3 | \
  26                                  CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10)
  27 /* 0x80840102 */
  28 #define CFG_SYS_DDR_TIMING_0    ((0 << TIMING_CFG0_RWT_SHIFT) | \
  29                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
  30                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
  31                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
  32                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
  33                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
  34                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  35                                  (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  36 /* 0x00220802 */
  37 #define CFG_SYS_DDR_TIMING_1    ((2 << TIMING_CFG1_PRETOACT_SHIFT) | \
  38                                  (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
  39                                  (2 << TIMING_CFG1_ACTTORW_SHIFT) | \
  40                                  (5 << TIMING_CFG1_CASLAT_SHIFT) | \
  41                                  (27 << TIMING_CFG1_REFREC_SHIFT) | \
  42                                  (2 << TIMING_CFG1_WRREC_SHIFT) | \
  43                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
  44                                  (2 << TIMING_CFG1_WRTORD_SHIFT))
  45 /* 0x3935D322 */
  46 #define CFG_SYS_DDR_TIMING_2    ((0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
  47                                  (31 << TIMING_CFG2_CPO_SHIFT) | \
  48                                  (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
  49                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
  50                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
  51                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
  52                                  (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  53 /* 0x0F9048CA */
  54 #define CFG_SYS_DDR_TIMING_3    0x00000000
  55 #define CFG_SYS_DDR_CLK_CNTL    DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  56 /* 0x02000000 */
  57 #define CFG_SYS_DDR_MODE        ((0x4440 << SDRAM_MODE_ESD_SHIFT) | (0x0232 << SDRAM_MODE_SD_SHIFT))
  58 /* 0x44400232 */
  59 #define CFG_SYS_DDR_MODE2       0x8000c000
  60 #define CFG_SYS_DDR_INTERVAL    ((800 << SDRAM_INTERVAL_REFINT_SHIFT) | \
  61                                  (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  62 #define CFG_SYS_DDR_CS0_BNDS    (CFG_SYS_DDR_SDRAM_BASE >> 8 | 0x0000001F)
  63
  64 #define CFG_SYS_DDR_SDRAM_CFG   (SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_32_BE)
  65 /* 0x43080000 */
  66 #define CFG_SYS_DDR_SDRAM_CFG2  0x00401000
  67
  68 /*
  69  * Initial RAM Base Address Setup
  70  */
  71 #define CFG_SYS_INIT_RAM_ADDR   (CONFIG_SYS_IMMR + 0x110000)
  72 #define CFG_SYS_INIT_RAM_SIZE   0x4000
  73
  74 /*
  75  * FLASH on the Local Bus
  76  */
  77 #define CFG_SYS_FLASH_BASE      0x40000000      /* FLASH base address */
  78 #define CFG_SYS_FLASH_SIZE      64              /* FLASH size is 64M */
  79
  80 /*
  81  * NAND
  82  */
  83 #define CFG_SYS_NAND_BASE       0xa0000000
  84
  85 /*
  86  * For booting Linux, the board info and command line data
  87  * have to be in the first 256 MB of memory, since this is
  88  * the maximum mapped by the Linux kernel during initialization.
  89  */
  90                                         /* Initial Memory map for Linux */
  91 #define CFG_SYS_BOOTMAPSZ       SZ_256M
  92
  93 /* Board names */
  94 #define CFG_BOARD_CMPCXXX       "cmpcpro"
  95 #define CFG_BOARD_MCR3000_2G    "mcrpro"
  96 #define CFG_BOARD_VGOIP         "vgoippro"
  97 #define CFG_BOARD_MIAE          "miaepro"
  98
  99 #endif  /* __CONFIG_H */