include/configs/cm_t43.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * cm_t43.h
   4  *
   5  * Copyright (C) 2015 Compulab, Ltd.
   6  */
   7
   8 #ifndef __CONFIG_CM_T43_H
   9 #define __CONFIG_CM_T43_H
  10
  11 #define CONFIG_MAX_RAM_BANK_SIZE        (2048 << 20)    /* 2GB */
  12 #define CONFIG_SYS_TIMERBASE            0x48040000      /* Use Timer2 */
  13
  14 #include <asm/arch/omap.h>
  15
  16 /* Serial support */
  17 #define CONFIG_SYS_NS16550_SERIAL
  18 #define CONFIG_SYS_NS16550_CLK          48000000
  19 #define CONFIG_SYS_NS16550_COM1         0x44e09000
  20 #if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
  21 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  22 #endif
  23
  24 /* NAND support */
  25 #define CONFIG_SYS_NAND_ONFI_DETECTION
  26 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  27 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
  28 #define CONFIG_SYS_NAND_OOBSIZE         64
  29 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
  30 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
  31 #define CONFIG_SYS_NAND_ECCSIZE         512
  32 #define CONFIG_SYS_NAND_ECCBYTES        14
  33 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW
  34 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
  35                                          CONFIG_SYS_NAND_PAGE_SIZE)
  36 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
  37                                          10, 11, 12, 13, 14, 15, 16, 17, \
  38                                          18, 19, 20, 21, 22, 23, 24, 25, \
  39                                          26, 27, 28, 29, 30, 31, 32, 33, \
  40                                          34, 35, 36, 37, 38, 39, 40, 41, \
  41                                          42, 43, 44, 45, 46, 47, 48, 49, \
  42                                          50, 51, 52, 53, 54, 55, 56, 57, }
  43
  44 /* CPSW Ethernet support */
  45 #define CONFIG_SYS_RX_ETH_BUFFER        64
  46
  47 /* Power */
  48 #define CONFIG_POWER_TPS65218
  49
  50 /* Enabling L2 Cache */
  51 #define CONFIG_SYS_L2_PL310
  52 #define CONFIG_SYS_PL310_BASE           0x48242000
  53
  54 /*
  55  * Since SPL did pll and ddr initialization for us,
  56  * we don't need to do it twice.
  57  */
  58
  59 #define CONFIG_HSMMC2_8BIT
  60
  61 #include <configs/ti_armv7_omap.h>
  62 #undef CONFIG_SYS_MONITOR_LEN
  63
  64 #define V_OSCK                          24000000  /* Clock output from T2 */
  65 #define V_SCLK                          (V_OSCK)
  66
  67 #define CONFIG_EXTRA_ENV_SETTINGS \
  68         "loadaddr=0x80200000\0" \
  69         "fdtaddr=0x81200000\0" \
  70         "bootm_size=0x8000000\0" \
  71         "autoload=no\0" \
  72         "console=ttyO0,115200n8\0" \
  73         "fdtfile=am437x-sb-som-t43.dtb\0" \
  74         "kernel=zImage-cm-t43\0" \
  75         "bootscr=bootscr.img\0" \
  76         "emmcroot=/dev/mmcblk0p2 rw\0" \
  77         "emmcrootfstype=ext4 rootwait\0" \
  78         "emmcargs=setenv bootargs console=${console} " \
  79                 "root=${emmcroot} " \
  80                 "rootfstype=${emmcrootfstype}\0" \
  81         "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
  82         "bootscript=echo Running bootscript from mmc ...; " \
  83                 "source ${loadaddr}\0" \
  84         "emmcboot=echo Booting from emmc ... && " \
  85                 "run emmcargs && " \
  86                 "load mmc 1 ${loadaddr} ${kernel} && " \
  87                 "load mmc 1 ${fdtaddr} ${fdtfile} && " \
  88                 "bootz ${loadaddr} - ${fdtaddr}\0"
  89
  90 #define CONFIG_BOOTCOMMAND \
  91         "mmc dev 0; " \
  92         "if mmc rescan; then " \
  93                 "if run loadbootscript; then " \
  94                         "run bootscript; " \
  95                 "fi; " \
  96         "fi; " \
  97         "mmc dev 1; " \
  98         "if mmc rescan; then " \
  99                 "run emmcboot; " \
 100         "fi;"
 101
 102 /* SPL defines. */
 103 #define CONFIG_SYS_SPL_ARGS_ADDR        (CONFIG_SYS_SDRAM_BASE + (128 << 20))
 104 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 105
 106 /* EEPROM */
 107
 108 #endif  /* __CONFIG_CM_T43_H */