4 * Copyright (C) 2015 Compulab, Ltd.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __CONFIG_CM_T43_H
10 #define __CONFIG_CM_T43_H
14 #define CONFIG_ARCH_CPU_INIT
15 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
16 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
18 #include <asm/arch/omap.h>
21 #define CONFIG_SYS_NS16550_SERIAL
22 #define CONFIG_SYS_NS16550_CLK 48000000
23 #define CONFIG_SYS_NS16550_COM1 0x44e09000
24 #ifdef CONFIG_SPL_BUILD
25 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
30 #define CONFIG_NAND_OMAP_ELM
31 #define CONFIG_SYS_NAND_ONFI_DETECTION
32 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
33 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
34 #define CONFIG_SYS_NAND_OOBSIZE 64
35 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
36 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
37 #define CONFIG_SYS_NAND_ECCSIZE 512
38 #define CONFIG_SYS_NAND_ECCBYTES 14
39 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
40 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
41 CONFIG_SYS_NAND_PAGE_SIZE)
42 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
43 10, 11, 12, 13, 14, 15, 16, 17, \
44 18, 19, 20, 21, 22, 23, 24, 25, \
45 26, 27, 28, 29, 30, 31, 32, 33, \
46 34, 35, 36, 37, 38, 39, 40, 41, \
47 42, 43, 44, 45, 46, 47, 48, 49, \
48 50, 51, 52, 53, 54, 55, 56, 57, }
50 /* CPSW Ethernet support */
51 #define CONFIG_DRIVER_TI_CPSW
53 #define CONFIG_BOOTP_DEFAULT
54 #define CONFIG_BOOTP_SEND_HOSTNAME
55 #define CONFIG_BOOTP_GATEWAY
56 #define CONFIG_NET_MULTI
57 #define CONFIG_PHY_GIGE
58 #define CONFIG_PHY_ATHEROS
60 #define CONFIG_SYS_RX_ETH_BUFFER 64
63 #define CONFIG_USB_HOST
64 #define CONFIG_USB_XHCI_OMAP
65 #define CONFIG_USB_STORAGE
66 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
67 #define CONFIG_OMAP_USB_PHY
68 #define CONFIG_AM437X_USB2PHY2_HOST
70 /* SPI Flash support */
71 #define CONFIG_TI_SPI_MMAP
72 #define CONFIG_SF_DEFAULT_SPEED 48000000
73 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
77 #define CONFIG_POWER_I2C
78 #define CONFIG_POWER_TPS65218
80 /* Enabling L2 Cache */
81 #define CONFIG_SYS_L2_PL310
82 #define CONFIG_SYS_PL310_BASE 0x48242000
83 #define CONFIG_SYS_CACHELINE_SIZE 32
86 * Since SPL did pll and ddr initialization for us,
87 * we don't need to do it twice.
89 #if !defined(CONFIG_SPL_BUILD)
90 #define CONFIG_SKIP_LOWLEVEL_INIT
93 #define CONFIG_HSMMC2_8BIT
95 #include <configs/ti_armv7_omap.h>
96 #undef CONFIG_SPL_OS_BOOT
97 #undef CONFIG_SPL_GPIO_SUPPORT
98 #undef CONFIG_SPL_NAND_SUPPORT
99 #undef CONFIG_SYS_MONITOR_LEN
100 #undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
102 #define CONFIG_ENV_SIZE (16 * 1024)
103 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
105 #define V_OSCK 24000000 /* Clock output from T2 */
106 #define V_SCLK (V_OSCK)
108 #define CONFIG_ENV_IS_IN_SPI_FLASH
109 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
110 #define CONFIG_ENV_OFFSET (768 * 1024)
111 #define CONFIG_ENV_SPI_MAX_HZ 48000000
113 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
115 /* Enhance our eMMC support / experience. */
116 #define CONFIG_CMD_GPT
117 #define CONFIG_EFI_PARTITION
119 #define CONFIG_EXTRA_ENV_SETTINGS \
120 "loadaddr=0x80200000\0" \
121 "fdtaddr=0x81200000\0" \
122 "bootm_size=0x8000000\0" \
124 "console=ttyO0,115200n8\0" \
125 "fdtfile=am437x-sb-som-t43.dtb\0" \
126 "kernel=zImage-cm-t43\0" \
127 "bootscr=bootscr.img\0" \
128 "emmcroot=/dev/mmcblk0p2 rw\0" \
129 "emmcrootfstype=ext4 rootwait\0" \
130 "emmcargs=setenv bootargs console=${console} " \
131 "root=${emmcroot} " \
132 "rootfstype=${emmcrootfstype}\0" \
133 "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
134 "bootscript=echo Running bootscript from mmc ...; " \
135 "source ${loadaddr}\0" \
136 "emmcboot=echo Booting from emmc ... && " \
138 "load mmc 1 ${loadaddr} ${kernel} && " \
139 "load mmc 1 ${fdtaddr} ${fdtfile} && " \
140 "bootz ${loadaddr} - ${fdtaddr}\0"
142 #define CONFIG_BOOTCOMMAND \
144 "if mmc rescan; then " \
145 "if run loadbootscript; then " \
150 "if mmc rescan; then " \
154 #define CONFIG_CONS_INDEX 1
157 #define CONFIG_SPL_TEXT_BASE 0x40300350
158 #define CONFIG_SPL_MAX_SIZE (64 * 1024)
159 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
160 #define CONFIG_SPL_POWER_SUPPORT
161 #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
162 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
163 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x480
164 #define CONFIG_SPL_SPI_SUPPORT
165 #define CONFIG_SPL_SPI_FLASH_SUPPORT
166 #define CONFIG_SPL_SPI_LOAD
167 #define CONFIG_SPL_I2C_SUPPORT
168 #define CONFIG_SPL_POWER_SUPPORT
171 #define CONFIG_CMD_EEPROM
172 #define CONFIG_ENV_EEPROM_IS_ON_I2C
173 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
174 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
176 #define CONFIG_SYS_EEPROM_SIZE 256
178 #define CONFIG_CMD_EEPROM_LAYOUT
179 #define CONFIG_EEPROM_LAYOUT_HELP_STRING "v2, v3"
181 #endif /* __CONFIG_CM_T43_H */